SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Offset | Length | Register Name | R5SS0 Physical Address | R5SS1 Physical Address |
---|---|---|---|---|
0h | 32 | ECC_AGG_CORE1_AGGR_REVISION | 5300 3000h | 5300 7000h |
8h | 32 | ECC_AGG_CORE1_ECC_VECTOR | 5300 3008h | 5300 7008h |
Ch | 32 | ECC_AGG_CORE1_MISC_STATUS | 5300 300Ch | 5300 700Ch |
10h | 32 | ECC_AGG_CORE1_ECC_WRAP_REVISION | 5300 3010h | 5300 7010h |
14h | 32 | ECC_AGG_CORE1_CONTROL | 5300 3014h | 5300 7014h |
18h | 32 | ECC_AGG_CORE1_ERROR_CTRL1 | 5300 3018h | 5300 7018h |
1Ch | 32 | ECC_AGG_CORE1_ERROR_CTRL2 | 5300 301Ch | 5300 701Ch |
20h | 32 | ECC_AGG_CORE1_ERROR_STATUS1 | 5300 3020h | 5300 7020h |
24h | 32 | ECC_AGG_CORE1_ERROR_STATUS2 | 5300 3024h | 5300 7024h |
28h | 32 | ECC_AGG_CORE1_ERROR_STATUS3 | 5300 3028h | 5300 7028h |
3Ch | 32 | ECC_AGG_CORE1_SEC_EOI_REG | 5300 303Ch | 5300 703Ch |
40h | 32 | ECC_AGG_CORE1_SEC_STATUS_REG0 | 5300 3040h | 5300 7040h |
80h | 32 | ECC_AGG_CORE1_SEC_ENABLE_SET_REG0 | 5300 3080h | 5300 7080h |
C0h | 32 | ECC_AGG_CORE1_SEC_ENABLE_CLR_REG0 | 5300 30C0h | 5300 70C0h |
13Ch | 32 | ECC_AGG_CORE1_DED_EOI_REG | 5300 313Ch | 5300 713Ch |
140h | 32 | ECC_AGG_CORE1_DED_STATUS_REG0 | 5300 3140h | 5300 7140h |
180h | 32 | ECC_AGG_CORE1_DED_ENABLE_SET_REG0 | 5300 3180h | 5300 7180h |
1C0h | 32 | ECC_AGG_CORE1_DED_ENABLE_CLR_REG0 | 5300 31C0h | 5300 71C0h |
200h | 32 | ECC_AGG_CORE1_AGGR_ENABLE_SET | 5300 3200h | 5300 7200h |
204h | 32 | ECC_AGG_CORE1_AGGR_ENABLE_CLR | 5300 3204h | 5300 7204h |
208h | 32 | ECC_AGG_CORE1_AGGR_STATUS_SET | 5300 3208h | 5300 7208h |
20Ch | 32 | ECC_AGG_CORE1_AGGR_STATUS_CLR | 5300 320Ch | 5300 720Ch |