SN74LV374AT

Name: SN74LV374AT
Brand: TI
SKU: SN74LV374AT
Price: 0.204 USD

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SN74LV374AT

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Data sheet

document-pdfAcrobat OCTAL EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS datasheet

SN74LV374AT

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Data sheet

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Product details

Number of channels

8

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

16

IOH (max) (mA)

-16

Supply current (max) (µA)

50

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

LV-AT

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL-Compatible CMOS

Output type

3-State

Clock frequency (max) (MHz)

70

IOL (max) (mA)

16

IOH (max) (mA)

-16

Supply current (max) (µA)

50

Features

Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

SOP (NS)

20

98.28 mm² 12.6 x 7.8

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd of 4.9 ns at 5 V
Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2.3 V
at V_CC = 5 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V_CC Operation
Typical t_pd of 4.9 ns at 5 V
Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 5 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot) >2.3 V
at V_CC = 5 V, T_A = 25°C
Support Mixed-Mode Voltage Operation on All Ports
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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