TLC320AD50

Name: TLC320AD50
Brand: TI
SKU: TLC320AD50
Price: 22.375 USD

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Einkanal-Codec mit Master-Slave-Funktion (3 Slaves) Und 89 dB Rauschabstand

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Datenblatt

document-pdfAcrobat Sigma-Delta Analog Interface Circuits With Master-Slave Function datasheet (Rev. E) (Englisch)

TLC320AD50

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Datenblatt

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Produktdetails

Number of ADC channels

1

Number of DAC channels

1

Analog inputs

2

Analog outputs

2

Sampling rate (max) (kHz)

22.05

Rating

Military

ADC SNR (typ) (dB)

0

DAC SNR (typ) (dB)

0

Operating temperature range (°C)

-40 to 85

Number of ADC channels

1

Number of DAC channels

1

Analog inputs

2

Analog outputs

2

Sampling rate (max) (kHz)

22.05

Rating

Military

ADC SNR (typ) (dB)

0

DAC SNR (typ) (dB)

0

Operating temperature range (°C)

-40 to 85

SOIC (DW)

28

184.37 mm² 17.9 x 10.3

General-purpose analog interface circuit for V.34+ modem and business audio applications
16-bit oversampling sigma-delta ADC and DAC
Serial port interface
Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
Typical 88-dB dynamic range
Test mode that includes a digital loopback test and analog loopback test
Programmable A/D and D/A conversion rate
Programmable input and output gain control
Maximum conversion rate: 22.05 kHz
Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
Power dissipation (P_D) of 120 mW rms typical in the operating mode
Hardware power-down mode to 7.5 mW
Internal reference voltage (V_ref)
Differential architecture throughout device
TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
2s complement data format
ALTDATA terminal provides data monitoring
Monitor amplifier to monitor input signals
On-chip phase locked loop (PLL)

General-purpose analog interface circuit for V.34+ modem and business audio applications
16-bit oversampling sigma-delta ADC and DAC
Serial port interface
Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC
Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC
Typical 88-dB dynamic range
Test mode that includes a digital loopback test and analog loopback test
Programmable A/D and D/A conversion rate
Programmable input and output gain control
Maximum conversion rate: 22.05 kHz
Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage
Power dissipation (P_D) of 120 mW rms typical in the operating mode
Hardware power-down mode to 7.5 mW
Internal reference voltage (V_ref)
Differential architecture throughout device
TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave
2s complement data format
ALTDATA terminal provides data monitoring
Monitor amplifier to monitor input signals
On-chip phase locked loop (PLL)

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from \x9640°C to 85°C.

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	Typ	Titel		Datum
*	Data sheet	Sigma-Delta Analog Interface Circuits With Master-Slave Function datasheet (Rev. E)		13 Okt 2000

TLC320AD50

Einkanal-Codec mit Master-Slave-Funktion (3 Slaves) Und 89 dB Rauschabstand

TLC320AD50

Produktdetails

Technische Dokumentation

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