Inicio Microcontroladores (MCU) y procesadores Procesadores basados en Arm
Inicio
Microcontroladores (MCU) y procesadores
Procesadores basados en Arm
NUEVO

TDA4AH-Q1

ACTIVO

SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad

Haga su pedido ahora
Hoja de datos
Errata

TDA4AH-Q1

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 2 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Security Cryptography, Debug security, Isolation firewalls, Memory protection, Secure boot, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
Arm CPU 8 Arm Cortex-A72 Arm (max) (MHz) 2000 Coprocessors MCU Island of 2 Arm Cortex-R5F (lockstep opt), SoC main of 6 Arm Corex-R5F (lockstep opt) CPU 64-bit Display type 1 EDP, 2 DSI, MIPI DPI Ethernet MAC 8-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 depth and motion accelerator, 2 video encode/decode accelerator, 2 vision pre-processing accelerators, 4 deep learning accelerators Security Cryptography, Debug security, Isolation firewalls, Memory protection, Secure boot, Trusted execution environment Rating Automotive Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 125
FCBGA (ALY) 1414 961 mm² 31 x 31

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

Processor cores:

  • Up to Four C7x floating point, vector DSP, up to 1.0 GHz, 320 GFLOPS, 1024 GOPS
  • Up to Four Deep-learning matrix multiply accelerator (MMAv2), up to 32 TOPS (8b) at 1.0 GHz
  • Two Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
  • Depth and Motion Processing Accelerators (DMPAC)
  • Eight Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz
    • 2MB shared L2 cache per quad-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex-A72 core
  • Eight Arm Cortex-R5F MCUs at up to 1.0 GHz
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm Cortex-R5F MCUs in isolated MCU subsystem
    • Six Arm Cortex-R5F MCUs in general compute partition
  • GPU IMG BXS-4-64, 256kB Cache, up to 800 MHz, 50 GFLOPS, 4 GTexels/s
  • Custom-designed interconnect fabric supporting near max processing entitlement

    Memory subsystem:

  • Up to 8MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • Up to Four External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • Up to 4x32-b bus with inline ECC up to 68 GB/s
  • General-Purpose Memory Controller (GPMC)
  • 3x512KB on-chip SRAM in MAIN domain, protected by ECC

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Safety-related certification
      • ISO 26262 planned
  • AEC-Q100 qualilfied on part number variants ending in Q1

    Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Integrated ethernet switch supporting up to 8 (TDA4xH) or 4 (TDA4xP) external ports
    • Two ports support 5Gb, 10Gb USXGMII/XFI
    • All ports support 1Gb, 2.5Gb SGMII
    • All ports can support QSGMII. A maximum of 2 (TDA4xH) or 1 (TDA4xP) QSGMII can be enabled and uses all 8 or 4 internal lanes
  • Up to 4x2-L/2x4L (TDA4xH) or 2x2L/1x4L (TDA4xP) PCI-Express (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • One USB 3.0 dual-role device (DRD) subsystem
    • Enhanced SuperSpeed Gen1 Port
    • Supports Type-C switching
    • Independently configurable as USB host, USB peripheral, or USB DRD
  • Three CSI2.0 4L RX plus Two CSI2.0 4L TX

    Ethernet:

  • Two RGMII/RMII interfaces

    Automotive interfaces:

  • Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Display subsystem:

  • Two DSI 4L TX (up to 2.5k)
  • One eDP/DP interface with Multi-Display Support (MST)
  • One DPI

    Audio interfaces:

  • Five Multichannel Audio Serial Port (MCASP) modules

    Video acceleration:

  • H.264/H.265 Encode/Decode, up to 960MP/s (TDA4xH) or 480MP/s (TDA4xP)

    Flash memory interfaces:

  • Embedded MultiMediaCard Interface ( eMMC™ 5.1)
  • One Secure Digital 3.0 / Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two independent flash interfaces configured as
    • One OSPI or HyperBus™ or QSPI flash interfaces, and
    • One QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 31 mm × 31 mm, 0.8-mm pitch, 1414-pin FCBGA (ALY), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.

The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at ADAS and Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the ADAS processor market. The unique combination high-performance compute, deep-learning engine, dedicated accelerators for signal and image processing in an functional safety compliant targeted architecture make the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 devices a great fit for several imaging, vision, radar, sensor fusion and AI applications such as: Robotics, Mobile machineries, Off-highway vehicle controller, Machine Vision, AI BOX, Gateways, Retail automation, Medical Imaging, and so on. The TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Key Performance Cores Overview

The “C7x” next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. A single instance of the new “MMAv2” deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated ADAS/AV hardware accelerators provide vision pre-processing plus distance and motion processing with no impact on system performance.

General Compute Cores and Integration Overview

Separate eight core cluster configuration of Arm Cortex-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Eight Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72’s unencumbered for applications. The integrated IMG BXS-4-64 GPU offers up to 50 GFLOPS to enable dynamic 3D rendering for enhanced viewing applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D/SIL-3 levels while the integrated security features protect data against modern day attacks. To enable systems requiring heavy data bandwidth, a PCIe hub and Gigabit Ethernet switch are included along with CSI-2 ports to support throughput for many sensor inputs. To further the integration, the TDA4VH-Q1 TDA4AH-Q1 TDA4VP-Q1 TDA4AP-Q1 family also includes an MCU island eliminating the need for an external system microcontroller.
filter Buscar otro/a Procesadores basados en Arm
Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Reemplazo con funcionalidad mejorada del dispositivo comparado
NUEVO TDA4AP-Q1 ACTIVO SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador Reduced CPU (50K DMIPS) and AI performance (24 TOPS), three LPDDR4 interfaces
NUEVO TDA4VP-Q1 ACTIVO SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador Reduced CPU (50K DMIPS) and AI performance (24 TOPS), includes GPU, video encode and decode
Funcionalidad similar a la del dispositivo comparado
TDA4VH-Q1 ACTIVO SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa Similar performance, includes GPU and video encode and decode acceleration

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 30
Tipo Título Fecha
* Data sheet TDA4VH-Q1, TDA4AH-Q1, TDA4VP-Q1, TDA4AP-Q1 Jacinto™ Processors datasheet (Rev. B) PDF | HTML 15 dic 2023
* Errata J784S4, TDA4AP, TDA4VP, TDA4AH, TDA4VH, AM69A Processors Silicon Revision 1.0 (Rev. B) PDF | HTML 24 jul 2024
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 ago 2024
User guide J784S4 J742S2 Technical Reference Manual (Rev. D) 24 jul 2024
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20 jun 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 jun 2024
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14 may 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 abr 2024
User guide SK-AM69 Processor Start Kit User's Guide (Rev. A) PDF | HTML 18 mar 2024
Technical article Building multicamera vision perception systems for ADAS domain controllers with integrated processors PDF | HTML 05 ene 2024
Technical article How to deliver current beyond 100 A to an ADAS processor PDF | HTML 04 ene 2024
Functional safety information J721E, J721S2, J7200, J784S4 MCAL TUV Certification 22 dic 2023
User guide J784S4, TDA4VH, TDA4AH, TDA4VP, TDA4AP, AM69 Power Estimation Tool User’s Guide PDF | HTML 07 dic 2023
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 nov 2023
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. C) 11 sep 2023
White paper Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13 mar 2023
User guide Powering Jacinto 7 SoC For Isolated Power Groups With TPS6594133A-Q1 + Dual HCPS PDF | HTML 01 mar 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 ene 2023
User guide Jacinto Processors TDA4AP/TDA4VP/TDA4AH/TDA4VH EVM Users Guide PDF | HTML 02 dic 2022
Functional safety information Jacinto™ 7 Safety Product Overview PDF | HTML 15 ago 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 abr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 abr 2022
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29 mar 2022
Technical article How to simplify your embedded edge AI application development PDF | HTML 28 ene 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 ene 2022
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 oct 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 jul 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 ene 2021
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 oct 2020
Application note OSPI Tuning Procedure PDF | HTML 08 jul 2020

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

J721EXENETXPANEVM — Módulo de evaluación TDA4xP-Q1 y TDA4xH-Q1 para SoC Jacinto™ 7 con expansión Ethernet cuádruple

The J721EXENETXPANEVM expands the capabilities of an evaluation module (EVM) with a quad Ethernet expansion card for evaluating Jacinto™ 7 system-on-a-chip (SoCs) in networking applications for both automotive and industrial markets. The quad-port Ethernet EVM is compatible J784S4XEVM and (...)

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

J784S4XEVM — Módulo de evaluación J784S4 para la familia TDA4xx de sistemas analíticos de campo lejano de sistema

The J784S4 evaluation module (EVM) is a platform for evaluating the TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 processors in vision analytics and networking applications throughout automotive and industrial markets. These processors perform particularly well in multicamera, sensor fusion and (...)

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

J7EXPCXEVM — Tarjeta de expansión de conmutador Gateway/Ethernet

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

Guía del usuario: PDF | HTML
No disponible en TI.com
Placa de evaluación

J7EXPEXEVM — Tarjeta de expansión de audio y pantalla

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our audio and display expansion card.
Guía del usuario: PDF | HTML
No disponible en TI.com
Sonda de depuración

TMDSEMU110-U — Sonda de depuración XDS110 JTAG

El XDS110 de Texas Instruments es una nueva clase de sonda de depuración (emulador) para procesadores integrados de TI. El XDS110 sustituye a la familia XDS100, al tiempo que es compatible con una mayor variedad de estándares (IEEE1149.1, IEEE1149.7, SWD) en un único pod. Además, todas las sondas (...)

Guía del usuario: PDF
No disponible en TI.com
Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-J784S4 — Linux® SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores basados en Arm
TDA4AP-Q1 — SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador TDA4VP-Q1 — SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador TDA4AH-Q1 — SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad TDA4VH-Q1 — SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa
Desarrollo de hardware
Placa de evaluación
J784S4XEVM — Módulo de evaluación J784S4 para la familia TDA4xx de sistemas analíticos de campo lejano de sistema
Opciones de descarga
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-QNX-J784S4 — QNX SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores basados en Arm
TDA4AP-Q1 — SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador TDA4VP-Q1 — SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador TDA4AH-Q1 — SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad TDA4VH-Q1 — SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa
Desarrollo de hardware
Placa de evaluación
J784S4XEVM — Módulo de evaluación J784S4 para la familia TDA4xx de sistemas analíticos de campo lejano de sistema
Opciones de descarga
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-J784S4 — RTOS SDK for TDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1

The J784S4 processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TTDA4AP-Q1, TDA4VP-Q1, TDA4AH-Q1 and TDA4VH-Q1 system-on-a-chip (SoCs) (...)

Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores basados en Arm
TDA4AH-Q1 — SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad TDA4VH-Q1 — SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa TDA4AP-Q1 — SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador TDA4VP-Q1 — SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador
Desarrollo de hardware
Placa de evaluación
J784S4XEVM — Módulo de evaluación J784S4 para la familia TDA4xx de sistemas analíticos de campo lejano de sistema
Opciones de descarga
IDE, configuración, compilador o depurador

C7000-CGT — Herramientas de generación de código para C7000: compilador

The TI C7000 C/C++ Compiler Tools support development of applications for TI C7000 Digital Signal Processor cores.

Code Composer Studio is the Integrated Development Environment (IDE) for TI embedded devices.  If you are looking to develop on a TI embedded device it is recommended to start (...)
Guía del usuario: PDF | HTML
View Options
IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

Productos y hardware compatibles

Productos y hardware compatibles

Este recurso de diseño es compatible con la mayoría de los productos de estas categorías.

Revise la página de detalles del producto para verificar la compatibilidad.
Iniciar Opciones de descarga
IDE, configuración, compilador o depurador

DDR-CONFIG-J784S4 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
Productos y hardware compatibles

Productos y hardware compatibles

Productos
Procesadores basados en Arm
TDA4AP-Q1 — SoC analítico automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, IA y codificador TDA4VP-Q1 — SoC automotriz para controladores de dominio L2, L3 con Arm® Cortex®-A72, gráficos, IA, coprocesador TDA4AH-Q1 — SoC analítico automotriz para fusión de sensores, controladores de dominio L2, L3 con IA y codificad TDA4VH-Q1 — SoC automotriz para fusión de sensores, controladores de dominio L2, L3 con gráficos, IA y coprocesa AM69 — Arm Cortex‑A72 de 8 núcleos y 64 bits con gráficos, PCIe Gen 3, Ethernet y USB 3.0 para uso gener AM69A — Sistema en chip (SoC) de visión 32 TOPS para entre 1 y 12 cámaras, robots móviles autónomos, visi
Desarrollo de hardware
Placa de evaluación
SK-AM69 — Kit de inicio AM69 y AM69A para IA de visión y procesadores de uso general
Iniciar
IDE, configuración, compilador o depurador

SAFETI_CQKIT — Kit de cualificación de compilador de seguridad

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
View Options
IDE, configuración, compilador o depurador

SYSCONFIG — Herramienta de configuración del sistema

SysConfig es una herramienta de configuración que simplifica la configuración de hardware y software y acelera el desarrollo de software.

SysConfig está disponible como parte de Code Composer Studio™, un entorno de desarrollo integrado, así como una aplicación independiente. Además, SysConfig (...)

View Options
Sistema operativo (SO)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

The QNX Neutrino® Realtime Operating System (RTOS) is a full-featured and robust RTOS designed to enable the next-generation of products for automotive, medical, transportation, military and industrial embedded systems. Microkernel design and modular architecture enable customers to create (...)
Desde: QNX Software Systems
Visitar el sitio del socio
Modelo de simulación

AM69 TDA4VH TDA4AH TDA4VP TDA4AP Thermal Model (Rev. A)

SPRM843A.ZIP (0 KB) - Thermal Model
Descargar
Modelo de simulación

AM69A,TDA4VH-Q1,TDA4AH-Q1,TDA4VP-Q1,TDA4AP-Q1 BSDL MODEL

SPRM840.ZIP (18 KB) - BSDL Model
Descargar
Modelo de simulación

IBIS Model for AM69 TDA4VH TDA4AH TDA4VP TDA4AP

SPRM836.ZIP (1497 KB) - IBIS Model
Descargar
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (ALY) 1414 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos