ホーム ロジックと電圧変換 専用ロジック IC
ホーム
ロジックと電圧変換
専用ロジック IC

CD74HC7046A

アクティブ

ハイスピード CMOS ロジック、VCO とロック・ディテクタ搭載、フェーズ・ロック・ループ

ご注文はこちら
データシート

CD74HC7046A

アクティブ
データシート ご注文はこちら

製品詳細

Technology family HC Bits (#) 1 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family HC Bits (#) 1 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Center Frequency of 18MHz (Typ) at VCC = 5V, Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Two Phase Comparators
    • Exclusive-OR
    • Edge-Triggered JK Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Zero Voltage Offset Due to Op-Amp Buffer
  • Operating Power-Supply Voltage Range
    • VCO Section...3V to 6V
    • Digital Section...2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control
    • Related Literature
      • AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A
  • Center Frequency of 18MHz (Typ) at VCC = 5V, Minimum Center Frequency of 12MHz at VCC = 4.5V
  • Choice of Two Phase Comparators
    • Exclusive-OR
    • Edge-Triggered JK Flip-Flop
  • Excellent VCO Frequency Linearity
  • VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
  • Minimal Frequency Drift
  • Zero Voltage Offset Due to Op-Amp Buffer
  • Operating Power-Supply Voltage Range
    • VCO Section...3V to 6V
    • Digital Section...2V to 6V
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Applications
    • FM Modulation and Demodulation
    • Frequency Synthesis and Multiplication
    • Frequency Discrimination
    • Tone Decoding
    • Data Synchronization and Conditioning
    • Voltage-to-Frequency Conversion
    • Motor-Speed Control
    • Related Literature
      • AN8823, CMOS Phase-Locked-Loop Application Using the CD74HC/HCT7046A and CD74HC/HCT7046A

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
filter その他の 専用ロジック IC を検索
ダウンロード

お客様が関心を持ちそうな類似品

open-in-new 代替品と比較
比較対象デバイスと類似の機能
LMK03318 アクティブ シングル PLL 搭載、超低ジッタ、クロック・ジェネレータ・ファミリ Low jitter, eight output clock generator with loss of signal and loss of lock detection

技術資料

star =TI が選定したこの製品の主要ドキュメント
結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
1 をすべて表示
種類 タイトル 最新の英語版をダウンロード 日付
* データシート CD74HC7046A, CD74HCT7046A データシート (Rev. C) 2003年 10月 16日

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブの拠点
  • 組み立てを実施した拠点

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

投稿されたすべてのフォーラムトピック (英語) を表示

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​