CY74FCT162652T

生産中止品

3 ステート出力、16 ビット バス・トランシーバ/レシーバ

CY74FCT162652T は生産中止品です。
この製品は生産中止品です。新規設計では代替品をご検討ください。
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製品詳細

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type TTL Features Balanced outputs, Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 16 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type TTL Output type TTL Features Balanced outputs, Damping resistors, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family FCT Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Ioff supports partial-power-down mode operation
  • Edge-rate control circuitry for significantly improved noise characteristics
  • Typical output skew < 250 ps
  • ESD > 2000V
  • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
  • Industrial temperature range of -40°C to +85°C
  • VCC = 5V ± 10%
  • CY74FCT16652T Features:
    • 64 mA sink current, 32 mA source current
    • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
  • CY74FCT162652T Features:
    • Balanced 24 mA output drivers
    • Reduced system switching noise
    • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C

  • Ioff supports partial-power-down mode operation
  • Edge-rate control circuitry for significantly improved noise characteristics
  • Typical output skew < 250 ps
  • ESD > 2000V
  • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
  • Industrial temperature range of -40°C to +85°C
  • VCC = 5V ± 10%
  • CY74FCT16652T Features:
    • 64 mA sink current, 32 mA source current
    • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25°C
  • CY74FCT162652T Features:
    • Balanced 24 mA output drivers
    • Reduced system switching noise
    • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA = 25°C

These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA\ control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines.

These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA\ control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 16-Bit Registered Transceivers データシート (Rev. B) 2001年 9月 19日

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点