SN54LVTH18502A

アクティブ

3.3 V ABT スキャン・テスト・デバイス、18 ビット ユニバーサル・トランシーバ付

製品詳細

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Military Operating temperature range (°C) -55 to 125
CFP (HV) 68 156.7504 mm² 12.52 x 12.52
  • Members of the Texas Instruments SCOPE™ Family of Testability Products
  • Members of the Texas Instruments Widebus™ Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
  • B-Port Outputs of ’LVTH182502A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPE™ Instruction Set
    - IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    - Parallel-Signature Analysis at Inputs
    - Pseudorandom Pattern Generation From Outputs
    - Sample Inputs/Toggle Outputs
    - Binary Count From Outputs
    - Device Identification
    - Even-Parity Opcodes
  • Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SCOPE, Widebus, and UBT are trademarks of Texas Instruments.

  • Members of the Texas Instruments SCOPE™ Family of Testability Products
  • Members of the Texas Instruments Widebus™ Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
  • B-Port Outputs of ’LVTH182502A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPE™ Instruction Set
    - IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    - Parallel-Signature Analysis at Inputs
    - Pseudorandom Pattern Generation From Outputs
    - Sample Inputs/Toggle Outputs
    - Binary Count From Outputs
    - Device Identification
    - Even-Parity Opcodes
  • Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SCOPE, Widebus, and UBT are trademarks of Texas Instruments.

The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of ’LVTH182502A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for operation from –40°C to 85°C.

The ’LVTH18502A and ’LVTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers, that combine with D-type latches and D-type flip-flops, they allow data to flow in the transparent, latched, or clocked modes. Another use is as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of ’LVTH182502A, which are designed to source or sink up to 12 mA, include 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18502A and SN54LVTH182502A are characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH18502A and SN74LVTH182502A are characterized for operation from –40°C to 85°C.

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A データシート (Rev. C) 2004年 6月 3日
* SMD SN54LVTH18502A SMD 5962-96811 2016年 6月 21日
アプリケーション・ノート Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
ユーザー・ガイド LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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アプリケーション・ノート 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
アプリケーション・ノート Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
セレクション・ガイド Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
アプリケーション・ノート LVT-to-LVTH Conversion 1998年 12月 8日
アプリケーション・ノート LVT Family Characteristics (Rev. A) 1998年 3月 1日
アプリケーション・ノート Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
アプリケーション・ノート Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
アプリケーション・ノート Live Insertion 1996年 10月 1日
アプリケーション・ノート Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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シミュレーション・モデル

BSDL Model of SN74LVTH18502A

SCTM029.ZIP (3 KB) - BSDL Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
CFP (HV) 68 Ultra Librarian

購入と品質

記載されている情報:
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  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
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  • ファブの拠点
  • 組み立てを実施した拠点

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