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SN74LVTH18514

アクティブ

3.3 V ABT スキャン・テスト・デバイス、20 ビット ユニバーサル・バス・トランシーバ付

ご注文はこちら
データシート

SN74LVTH18514

アクティブ
データシート ご注文はこちら

製品詳細

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 64 137.7 mm² 17 x 8.1
  • Members of the Texas Instruments (TITM) SCOPETM Family of Testability Products
  • Members of the TI WidebusTM Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • B-Port Outputs of 'LVTH182514 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPETM Instruction Set
    • IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • Package Options Include 64-Pin Plastic Thin Shrink Small-Outline (DGG) and 64-Pin Ceramic Dual Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings

    SCOPE, Widebus, UBT, and TI are trademarks of Texas Instruments Incorporated.
  • Members of the Texas Instruments (TITM) SCOPETM Family of Testability Products
  • Members of the TI WidebusTM Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • B-Port Outputs of 'LVTH182514 Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPETM Instruction Set
    • IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • Package Options Include 64-Pin Plastic Thin Shrink Small-Outline (DGG) and 64-Pin Ceramic Dual Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings

    SCOPE, Widebus, UBT, and TI are trademarks of Texas Instruments Incorporated.

The 'LVTH18514 and 'LVTH182514 scan test devices with 20-bit universal bus transceivers are members of the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), clock-enable (CLKENAB\ and CLKENBA\), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKENAB\ is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB\ is low, A data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, CLKENBA\, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of 'LVTH182514, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18514 and SN54LVTH182514 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH18514 and SN74LVTH182514 are characterized for operation from -40°C to 85°C.

A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA\, LEBA, CLKENBA\, and CLKBA.

Output level before the indicated steady-state input conditions were established

The 'LVTH18514 and 'LVTH182514 scan test devices with 20-bit universal bus transceivers are members of the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), clock-enable (CLKENAB\ and CLKENBA\), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKENAB\ is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and CLKENAB\ is low, A data is stored on a low-to-high transition of CLKAB. When OEAB\ is low, the B outputs are active. When OEAB\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA\, LEBA, CLKENBA\, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of 'LVTH182514, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18514 and SN54LVTH182514 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH18514 and SN74LVTH182514 are characterized for operation from -40°C to 85°C.

A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA\, LEBA, CLKENBA\, and CLKBA.

Output level before the indicated steady-state input conditions were established
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種類 タイトル 最新の英語版をダウンロード 日付
* データシート 3.3-V ABT Scan Test Devices With 20-Bit Universal Bus Transceivers データシート (Rev. C) 1998年 3月 29日
アプリケーション・ノート Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
アプリケーション・ノート An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
ユーザー・ガイド LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
EVM ユーザー ガイド (英語) LASP Demo Board User's Guide 2005年 11月 1日
アプリケーション・ノート Programming CPLDs Via the 'LVT8986 LASP 2005年 11月 1日
アプリケーション・ノート Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
アプリケーション・ノート TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
アプリケーション・ノート 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
アプリケーション・ノート Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
セレクション・ガイド Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
アプリケーション・ノート LVT-to-LVTH Conversion 1998年 12月 8日
アプリケーション・ノート LVT Family Characteristics (Rev. A) 1998年 3月 1日
アプリケーション・ノート Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
アプリケーション・ノート Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
アプリケーション・ノート Live Insertion 1996年 10月 1日
アプリケーション・ノート Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計および開発

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シミュレーション・モデル

BSDL Model of SN74LVTH18514

SCTM034.ZIP (3 KB) - BSDL Model
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シミュレーション・モデル

SN74LVTH18514 IBIS Model

SCEM092.ZIP (16 KB) - IBIS Model
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記載されている情報：
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  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
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