홈 마이크로컨트롤러(MCU) 및 프로세서 Arm 기반 프로세서
홈
마이크로컨트롤러(MCU) 및 프로세서
Arm 기반 프로세서

AM5K2E02

활성

Sitara™ 프로세서: 듀얼 Arm Cortex-A15

지금 주문
데이터 시트
정오표

AM5K2E02

활성
데이터 시트 지금 주문

제품 상세 정보

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² 27 x 27
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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기술 자료

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52개 모두 보기
유형 직함 날짜
* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 2015/03/11
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 2015/08/20
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/07/07
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019/06/04
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019/05/17
Application note KeyStone II DDR3 interface bring-up 2019/03/07
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/09/24
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017/08/21
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/08/14
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/07/26
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 2017/06/14
Application note Clocking Spreadsheet for K2E Device Family 2017/01/26
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016/07/27
Application note Power Management of KS2 Device (Rev. C) 2016/07/15
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015/12/22
Application note Keystone II DDR3 Debug Guide 2015/10/16
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015/05/06
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015/04/28
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/04/09
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015/03/27
White paper Save power and costs with TI's K2E on-chip networking features 2015/03/25
Application note Keystone II DDR3 Initialization 2015/01/26
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/09/04
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 2014/08/25
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014/08/19
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014/08/19
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 2014/08/14
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014/08/13
Application note Hardware Design Guide for KeyStone II Devices 2014/03/24
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013/09/30
User guide Debug and Trace for KeyStone II Devices User's Guide 2013/07/26
User guide ARM Bootloader User Guide for KeyStone II Devices 2013/07/21
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/06/28
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013/05/28
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012/11/12
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 2012/11/09
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 2012/11/09
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 2012/11/05
User guide ARM CorePac User Guide for KeyStone II Devices 2012/10/31
Application note Multicore Programming Guide (Rev. B) 2012/08/29
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/03/30
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/03/27
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/03/22
Application note PCIe Use Cases for KeyStone Devices 2011/12/13
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/09/02
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/05/24
User guide C66x DSP Cache User's Guide 2010/11/09
Application note Clocking Design Guide for KeyStone Devices 2010/11/09
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/09
Application note Optimizing Loops on the C66x DSP 2010/11/09
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 2010/11/09
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010/11/09

설계 및 개발

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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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개발 키트

EVMK2EX — K2E 개발 보드

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

사용 설명서: PDF
TI.com에서 구매 불가
소프트웨어 개발 키트(SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
66AK2E05 — 고성능 멀티 코어 DSP+Arm - 4x Arm A15 코어, 1x C66x DSP 코어, NetCP, 10GbE 66AK2H06 — 고성능 멀티 코어 DSP+Arm - 2x Arm A15 코어, 4x C66x DSP 코어 66AK2H12 — 고성능 멀티 코어 DSP+Arm - Arm A15 코어 4개, C66x DSP 코어 8개 66AK2H14 — 고성능 멀티코어 DSP+Arm - 4x Arm A15 코어, 8x C66x DSP 코어, 10GbE AM5K2E02 — Sitara™ 프로세서: 듀얼 Arm Cortex-A15 AM5K2E04 — Sitara 프로세서: 쿼드 Arm Cortex-A15
DSP(디지털 신호 프로세서)
66AK2L06 — 멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
66AK2E05 — 고성능 멀티 코어 DSP+Arm - 4x Arm A15 코어, 1x C66x DSP 코어, NetCP, 10GbE AM5K2E02 — Sitara™ 프로세서: 듀얼 Arm Cortex-A15 AM5K2E04 — Sitara 프로세서: 쿼드 Arm Cortex-A15
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
66AK2E05 — 고성능 멀티 코어 DSP+Arm - 4x Arm A15 코어, 1x C66x DSP 코어, NetCP, 10GbE AM5K2E02 — Sitara™ 프로세서: 듀얼 Arm Cortex-A15 AM5K2E04 — Sitara 프로세서: 쿼드 Arm Cortex-A15
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
66AK2E05 — 고성능 멀티 코어 DSP+Arm - 4x Arm A15 코어, 1x C66x DSP 코어, NetCP, 10GbE AM5K2E02 — Sitara™ 프로세서: 듀얼 Arm Cortex-A15 AM5K2E04 — Sitara 프로세서: 쿼드 Arm Cortex-A15
다운로드 옵션
IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
시뮬레이션 모델

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL Model
다운로드
시뮬레이션 모델

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS Model
다운로드
시뮬레이션 모델

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Thermal Model
다운로드
시뮬레이션 모델

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Power Model
다운로드
시뮬레이션 모델

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 수출 승인 필요(1분)
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계산 툴

CLOCKTREETOOL — Sitara, 오토모티브, 비전 분석 및 디지털 신호 프로세서용 클록 트리 툴

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
사용 설명서: PDF
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회로도

66AK2E05 66AK2E02 AM5K2E04 AM5K2E02 ABD OrCAD Symbols

SPRR197.ZIP (99 KB)
다운로드
레퍼런스 디자인

TIDEP0042 — TPS544C25 및 PMBus를 사용하여 K2E를 위한 AVS SmartReflex 코어 전압 생성 레퍼런스 디자인

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0041 — K2E용 AVS SmartReflex 코어 전압, PMBus 생성 레퍼런스 디자인

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0031 — PMBus 지원 UCD9090을 사용한 K2E용 전원 시퀀싱

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0026 — K2E 클록 생성 레퍼런스 디자인

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)
Design guide: PDF
회로도: PDF
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (ABD) 1089 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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