홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

66AK2L06

활성

멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)

지금 주문
데이터 시트
정오표

66AK2L06

활성
데이터 시트 지금 주문

제품 상세 정보

DSP type 4 C66x DSP (max) (MHz) 1200 CPU 32-/64-bit Operating system Integrity, Linux, SYS/BIOS, VxWorks Security Cryptographic acceleration, Device identity, Secure boot Ethernet MAC 4-port 1Gb Switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 4 C66x DSP (max) (MHz) 1200 CPU 32-/64-bit Operating system Integrity, Linux, SYS/BIOS, VxWorks Security Cryptographic acceleration, Device identity, Secure boot Ethernet MAC 4-port 1Gb Switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) 0 to 0
FCBGA (CMS) 900 625 mm² 25 x 25
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.
filter 기타 DSP(디지털 신호 프로세서) 찾기
다운로드 스크립트와 함께 비디오 보기 동영상
Support through a third party

This product does not have ongoing direct design support from TI. For support while working through your design, you may contact the following third party: Azcom Technology.

기술 자료

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67개 모두 보기
유형 직함 날짜
* Data sheet 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet 2015/04/21
* Errata 66AK2Lxx Multicore DSP+ARM KeyStone II SOC (Silicon Revision 1.0) 2015/04/20
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/07/07
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021/06/25
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019/06/04
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017/08/21
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/08/14
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/07/26
Design guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 2016/09/23
Application note Keystone EDMA FAQ 2016/09/01
Third party document Download XEVMK2LX schematics, bill of materials and design guide 2016/08/03
Third party document XEVMK2LX Quick Setup Guide 2016/08/03
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016/07/27
Application note Power Management of KS2 Device (Rev. C) 2016/07/15
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 2016/06/20
Technical article How to complete your RF sampling solution PDF | HTML 2016/05/18
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016/04/13
Technical article Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more PDF | HTML 2016/03/02
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016/02/23
Application note TI DSP Benchmarking 2016/01/13
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015/12/22
White paper Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce 2015/12/17
Technical article Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment? PDF | HTML 2015/12/02
White paper Optimizing your test and measurement solution by leveraging the most integrated 2015/11/03
Design guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 2015/10/22
Application note Keystone II DDR3 Debug Guide 2015/10/16
Application note System solution for avionics & defense 2015/09/23
Application note TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC Mode 2015/09/18
Technical article Summertime showdown: DSPs vs FPGAs PDF | HTML 2015/07/09
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015/05/06
Technical article Wireless infrastructure - Now simpler and more accessible! PDF | HTML 2015/05/05
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015/04/28
Product overview 66AK2L06 SoC Product Bulletin 2015/04/15
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/04/09
White paper Optimizing synthetic aperture radar design with TI's integrated 66AK2L06 SoC 2015/04/09
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015/03/27
User guide Digital Front End (DFE) for Keystone II Devices User's Guide (Rev. A) 2015/03/23
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 2015/03/19
User guide Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A) 2015/02/11
Application note Keystone II DDR3 Initialization 2015/01/26
User guide IQN2 for KeyStone II Devices User's Guide (Rev. A) 2014/10/01
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/09/04
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014/08/19
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014/08/19
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014/08/13
Application note Hardware Design Guide for KeyStone II Devices 2014/03/24
User guide Debug and Trace for KeyStone II Devices User's Guide 2013/07/26
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013/07/15
User guide C66x CorePac User's Guide (Rev. C) 2013/06/28
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/06/28
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012/11/12
User guide ARM CorePac User Guide for KeyStone II Devices 2012/10/31
Application note Multicore Programming Guide (Rev. B) 2012/08/29
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 2012/04/24
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/03/30
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/03/27
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/03/22
Application note PCIe Use Cases for KeyStone Devices 2011/12/13
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/09/02
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/05/24
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011/05/19
User guide C66x CPU and Instruction Set Reference Guide 2010/11/09
User guide C66x DSP Cache User's Guide 2010/11/09
Application note Clocking Design Guide for KeyStone Devices 2010/11/09
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/09
Application note Optimizing Loops on the C66x DSP 2010/11/09

설계 및 개발

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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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소프트웨어 개발 키트(SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
66AK2E05 — 고성능 멀티 코어 DSP+Arm - 4x Arm A15 코어, 1x C66x DSP 코어, NetCP, 10GbE 66AK2H06 — 고성능 멀티 코어 DSP+Arm - 2x Arm A15 코어, 4x C66x DSP 코어 66AK2H12 — 고성능 멀티 코어 DSP+Arm - Arm A15 코어 4개, C66x DSP 코어 8개 66AK2H14 — 고성능 멀티코어 DSP+Arm - 4x Arm A15 코어, 8x C66x DSP 코어, 10GbE AM5K2E02 — Sitara™ 프로세서: 듀얼 Arm Cortex-A15 AM5K2E04 — Sitara 프로세서: 쿼드 Arm Cortex-A15
DSP(디지털 신호 프로세서)
66AK2L06 — 멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-K2L — Linux Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
66AK2L06 — 멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-K2L — Linux-RT Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
66AK2L06 — 멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-RTOS-K2L — RTOS Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
66AK2L06 — 멀티코어 DSP+ARM KeyStone II 시스템온칩(SoC)
다운로드 옵션
소프트웨어 개발 키트(SDK)

RFSDK — 무선 주파수 소프트웨어 개발자 키트(RFSDK)

Texas Instruments Radio Frequency Software Development Kit (RFSDK) is a collection of highly optimized APIs and highly abstracted commands to control, configure and manage the JESD204B interface, digital front end (DFE), analog front end (AFE) and high speed data converters (ADC/DAC). The RFSDK (...)
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드라이버 또는 라이브러리

MATHLIB — 부동 소수점 디바이스용 DSP 수학 라이브러리

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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드라이버 또는 라이브러리

SPRC264 — TMS320C5000/6000 이미지 라이브러리(IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
사용 설명서: PDF
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드라이버 또는 라이브러리

SPRC265 — TMS320C6000 DSP 라이브러리(DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
사용 설명서: PDF
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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
소프트웨어 코덱

C66XCODECS — 코덱 - 비디오, 음성 - C66x 기반 디바이스

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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시뮬레이션 모델

66AK2L06 Power Consumption Model

SPRM656.ZIP (169 KB) - Power Model
다운로드
시뮬레이션 모델

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 수출 승인 필요(1분)
lock 다운로드
시뮬레이션 모델

TCI6632K2L TCI6631K2L and TCI6630K2L AAW IBIS Model

SPRM589.ZIP (3192 KB) - IBIS Model
다운로드
레퍼런스 디자인

TIDEP0081 — ADC32RF80에 66AK2L06 JESD204B 연결을 사용하여 광대역 리시버 설계 레퍼런스 디자인

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0060 — DSP+ARM SoC를 사용하여 최적화된 레이더 시스템 레퍼런스 디자인

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0034 — 광대역 ADC 및 DAC에 JESD204B가 연결된 66AK2L06 DSP+ARM 프로세서

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
Design guide: PDF
회로도: PDF
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (CMS) 900 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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