전원 관리 게이트 드라이버 절연 게이트 드라이버

ISO5852S

활성

분할 출력, STO 및 보호 기능을 지원하는 5.7kVrms, 2.5A/5A 단일 채널 절연 게이트 드라이버

제품 상세 정보

Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
Number of channels 1 Isolation rating Reinforced Withstand isolation voltage (VISO) (Vrms) 5700 Working isolation voltage (VIOWM) (Vrms) 2121 Transient isolation voltage (VIOTM) (VPK) 8000 Power switch IGBT, MOSFET Peak output current (A) 5 Features Active miller clamp, Fault reporting, Power good, Short circuit protection, Soft turn-off, Split output Output VCC/VDD (max) (V) 30 Output VCC/VDD (min) (V) 15 Input supply voltage (min) (V) 2.25 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.076 Input threshold CMOS Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 2121 Rise time (ns) 18 Fall time (ns) 20 Undervoltage lockout (typ) (V) 12
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification
  • 100-kV/µs Minimum Common-Mode Transient Immunity (CMTI) at V CM = 1500 V
  • Split Outputs to Provide 2.5-A Peak Source and 5-A Peak Sink Currents
  • Short Propagation Delay: 76 ns (Typ), 110 ns (Max)
  • 2-A Active Miller Clamp
  • Output Short-Circuit Clamp
  • Soft Turn-Off (STO) during Short Circuit
  • Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
  • Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
  • Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
  • 2.25-V to 5.5-V Input Supply Voltage
  • 15-V to 30-V Output Driver Supply Voltage
  • CMOS Compatible Inputs
  • Rejects Input Pulses and Noise Transients Shorter Than 20 ns
  • Operating Temperature: –40°C to +125°C Ambient
  • Isolation Surge Withstand Voltage 12800-V PK
  • Safety-Related Certifications:
    • 8000-V PK V IOTM and 2121-V PK V IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
    • 5700-V RMS Isolation for 1 Minute per UL 1577
    • CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
    • TUV Certification per EN 61010-1 and EN 60950-1
    • GB4943.1-2011 CQC Certification

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

The ISO5852S device is a 5.7-kV RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 µs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V EE2, the gate-driver output is pulled hard to the V EE2 potential, turning the IGBT immediately off.

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

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기술 자료

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29개 모두 보기
유형 직함 날짜
* Data sheet ISO5852S High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features datasheet (Rev. C) PDF | HTML 2023/05/30
Certificate VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. S) 2024/02/29
Application note Digital Isolator Design Guide (Rev. G) PDF | HTML 2023/09/13
User guide UCC217xx and ISO5x5x Half-Bridge EVM User's Guide for Wolfspeed 1200-V SiC 2023/09/01
White paper Circuit Board Insulation Design According to IEC60664 for Motor Drive Apps PDF | HTML 2023/08/31
Certificate ISO5451 CQC Certificate of Product Certification 2023/08/16
Certificate TUV Certificate for Isolation Devices (Rev. K) 2022/08/05
Certificate UL Certificate of Compliance File E181974 Vol 4 Sec 6 (Rev. P) 2022/08/05
Application note Comparative Analysis of Two Different Methods for Gate-Drive Current Boosting (Rev. A) PDF | HTML 2022/02/17
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML 2021/12/16
Certificate CSA Certification (Rev. Q) 2021/06/14
Application brief External Gate Resistor Selection Guide (Rev. A) 2020/02/28
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 2020/02/28
Functional safety information Isolation in AC Motor Drives: Understanding the IEC 61800-5-1 Safety Standard (Rev. A) 2019/09/19
Technical article Designing highly efficient, powerful and fast EV charging stations PDF | HTML 2019/08/06
Analog Design Journal Pushing the envelope with high-performance digital-isolation technology (Rev. A) 2018/08/22
User guide ISO5852SDW Driving and Protecting SiC and IGBT Power Modules 2018/05/24
Functional safety information Isolation in solar power converters: Understanding the IEC62109-1 safety standar (Rev. A) 2018/05/18
Technical article Why capacitive isolation: a vital building block for sensors in smart cities PDF | HTML 2018/01/16
Application note Isolation Glossary (Rev. A) 2017/09/19
Technical article Understanding isolator failure modes for safe isolation PDF | HTML 2016/03/28
Technical article 7 steps to choose the right isolators for AC motor-drive applications PDF | HTML 2015/11/24
Analog Design Journal 4Q 2015 Analog Applications Journal 2015/10/30
Analog Design Journal Common-mode transient immunity for isolated gate drivers 2015/10/30
Analog Design Journal Pushing the envelope with high-performance digital-isolation technology 2015/10/30
EVM User's guide ISO5852S Evaluation Module User's Guide (Rev. A) 2015/09/08
White paper Understanding electromagnetic compliance tests in digital isolators 2014/10/17
White paper High-voltage reinforced isolation: Definitions and test methodologies 2014/10/16
Application note Shelf-Life Evaluation of Lead-Free Component Finishes 2004/05/24

설계 및 개발

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평가 보드

ISO5852SDWEVM-017 — SiC 및 IGBT 전원 모듈용 구동 및 보호 평가 보드

The ISO5852SDWEVM-017 is a compact, dual chanel isolated gate driver board providing drive, bias voltages, protection and diagnostic needed for half-bridge Sic MOSFET and IGBT Power Modules in standard 62-mm package. This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in (...)

사용 설명서: PDF
TI.com에서 구매 불가
평가 보드

ISO5852SEVM — 강화 절연 IGBT 게이트 드라이버 평가 모듈

This evaluation module, featuring ISO5852S reinforced isolated gate driver device, allows designers to evaluate device AC and DC performance with a pre-populated 1-nF load or with a user-installed IGBT in either of the standard TO-247 or TO-220 packages.

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

ISO5852S IBIS Model

SLLM283.ZIP (33 KB) - IBIS Model
시뮬레이션 모델

ISO5852S PSpice Transient Model (Rev. A)

SLLM300A.ZIP (232 KB) - PSpice Model
시뮬레이션 모델

ISO5852S TINA-TI Reference Design

SLLM436.TSC (1537 KB) - TINA-TI Reference Design
시뮬레이션 모델

ISO5852S TINA-TI SPICE Model

SLLM435.ZIP (31 KB) - TINA-TI Spice Model
시뮬레이션 모델

ISO5852S Unencrypted PSPICE Transient Model

SLLM446.ZIP (4 KB) - PSpice Model
설계 툴

SLLR117 ISO5852SDWEVM-017 Design Files

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
절연 게이트 드라이버
ISO5852S 분할 출력, STO 및 보호 기능을 지원하는 5.7kVrms, 2.5A/5A 단일 채널 절연 게이트 드라이버
하드웨어 개발
평가 보드
ISO5852SDWEVM-017 SiC 및 IGBT 전원 모듈용 구동 및 보호 평가 보드
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
레퍼런스 디자인

TIDA-01606 — 10kW, 양방향 3상 3레벨(T형) 인버터 및 PFC 레퍼런스 설계

This verified reference design provides an overview on how to implement a three-level three-phase SiC based DC:AC T-type inverter stage. Higher switching frequency of 50KHz reduces the size of magnetics for the filter design and enables higher power density. The use of SiC MOSFETs with switching (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDA-00195 — 3상 인버터 시스템용 절연 IGBT 게이트 드라이버 평가 플랫폼 레퍼런스 디자인

The TIDA-00195 reference design consists of a 22kW power stage with TI’s new reinforced isolated IGBT gate driver ISO5852S intended for motor control in various applications. This design allows performance evaluation of the ISO5852S in 3-phase inverter incorporating 1200V rated IGBT modules (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDA-01599 — AC 인버터 및 서보 드라이브를 위한 중복 듀얼 채널 STO(Safe Torque Off) 레퍼런스 설계

이 레퍼런스 설계는 CMOS 입력 절연 IGBT 게이트 드라이버를 지원하는 3상 인버터용 STO(Safe Torque Off) 서브시스템을 설명합니다. STO 하위 시스템은 하드웨어 내결함성이 1(HFT=1)인 이중 채널 아키텍처(1oo2)를 사용합니다. 이 기능은 트립 개념의 에너지를 차단한 후에 구현됩니다. 듀얼 STO 입력(STO_1 및 STO_2)이 LOW로 전환되면 6개의 절연 IGBT 게이트 드라이버의 1차 및 2차측 해당 전원 공급 장치가 부하 스위치를 통해 차단됩니다. 이렇게 하면 모터를 제어하고 에너지를 충전할 (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDA-00917 — 단락 보호 및 전류 버퍼 기능을 갖춘 병렬 IGBT를 위한 게이트 드라이버 레퍼런스 디자인

Paralleling insulated-gate bipolar transistors (IGBTs) becomes necessary for power conversion equipment with higher output power ratings, where a single IGBT cannot provide the required load current. This reference design implements a reinforced isolated IGBT gate control module to drive (...)
Design guide: PDF
회로도: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (DW) 16 Ultra Librarian

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  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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  • 팹 위치
  • 조립 위치

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