홈 마이크로컨트롤러(MCU) 및 프로세서 DSP(디지털 신호 프로세서)
홈
마이크로컨트롤러(MCU) 및 프로세서
DSP(디지털 신호 프로세서)

TMS320C6657

활성

고성능 듀얼 코어 C66x 고정 및 부동 소수점 DSP - 최대 1.25GHz, 2UART

지금 주문
데이터 시트
정오표

TMS320C6657

활성
데이터 시트 지금 주문

제품 상세 정보

DSP type 2 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
DSP type 2 C66x DSP (max) (MHz) 1000, 1250 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (CZH) 625 441 mm² 21 x 21 FCBGA (GZH) 625 441 mm² 21 x 21
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C
  • One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed- and Floating-Point CPU Core
      • 40 GMAC per Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP per Core for Floating Point @ 1.25 GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for C6657)
    • Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24, 2.5, 3.125, and 5 GBaud Operation Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Up to Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

The C665x are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 1.25 GHz. For developers of a broad range of applications, both C665x DSPs enable a platform that is power-efficient and easy to use. In addition, the C665x DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 40 GMACS per core and 20 GFLOPS per core (@1.25 GHz operating frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C665x DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. The device also integrates 1024KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1333 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and Gigabit Ethernet. This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, a 40-Gbaud full-duplex interface called HyperLink is included.

The C665x devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that lets SoCs work in tandem. The low-protocol overhead and high throughput of HyperLink make an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
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78개 모두 보기
유형 직함 날짜
* Data sheet TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. D) PDF | HTML 2019/09/04
* Errata TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C) 2016/05/19
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022/07/07
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021/06/25
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021/05/19
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020/06/01
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019/06/11
Application note Keystone Bootloader Resources and FAQ 2019/05/29
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019/05/17
Application note Hardware Design Guide for KeyStone Devices (Rev. D) 2019/03/21
Application note KeyStone I DDR3 interface bring-up 2019/03/06
White paper Designing professional audio mixers for every scenario 2018/06/28
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/08/14
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017/07/26
Application note PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A) 2017/05/19
Application note Processor SDK RTOS Audio Benchmark Starter Kit 2017/04/12
Application note Power Consumption Summary for KeyStone C66x Devices (Rev. B) 2017/02/02
Application note KeyStone I DDR3 Initialization (Rev. E) 2016/10/28
Application note Keystone NDK FAQ 2016/10/03
Product overview TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A) 2016/05/23
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016/04/13
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016/02/23
Application note TI DSP Benchmarking 2016/01/13
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015/08/13
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015/05/06
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015/04/09
White paper TI’s processors leading the way in embedded analytics 2015/03/03
User guide DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E) 2015/01/20
Application note TI Keystone DSP Hyperlink SerDes IBIS-AMI Models 2014/10/09
Application note TI Keystone DSP PCIe SerDes IBIS-AMI Models 2014/10/09
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014/09/04
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 2014/09/03
More literature KeyStone Lab Manual - Training 2014/06/05
User guide System Analyzer User's Guide (Rev. F) 2013/11/18
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013/09/30
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013/07/15
White paper Accelerating high-performance computing development with Desktop Linux SDK 2013/07/08
User guide C66x CorePac User's Guide (Rev. C) 2013/06/28
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013/06/28
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013/05/28
Product overview OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A) 2012/11/05
Application note SerDes Implementation Guidelines for KeyStone I Devices 2012/10/31
Product overview TMS320C66x high-performance multicore DSPs for video surveillance 2012/09/06
Application note Multicore Programming Guide (Rev. B) 2012/08/29
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012/08/21
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012/08/21
User guide Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices 2012/07/12
User guide Universal Parallel Port (uPP) for KeyStone Architecture User's Guide 2012/06/11
User guide Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices 2012/05/25
White paper Leveraging multicore processors for machine vision applications 2012/05/09
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 2012/04/24
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012/03/30
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012/03/27
White paper Superior performance at breakthrough size, weight & power 2012/03/26
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012/03/22
White paper Maximizing Multicore Efficiency with Navigator Runtime 2012/02/23
Application note PCIe Use Cases for KeyStone Devices 2011/12/13
User guide Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A) 2011/10/15
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide Debug and Trace for KeyStone I Devices User's Guide (Rev. A) 2011/09/22
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011/09/02
White paper KeyStone Multicore SoC Tool Suite: one platform for all needs 2011/06/17
User guide Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A) 2011/06/10
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011/05/24
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011/05/19
Application note TMS320C66x DSP Generation of Devices (Rev. A) 2011/04/25
White paper Software-Based Ultrasound Phase Rotation Beamforming on Multicore DSP 2011/03/16
White paper Software-Based Ultrasound Beamforming on Multicore DSPs 2011/03/06
White paper KeyStone Memory Architecture White Paper (Rev. A) 2010/12/21
User guide Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide 2010/11/18
User guide C66x CPU and Instruction Set Reference Guide 2010/11/09
User guide C66x DSP Cache User's Guide 2010/11/09
Application note Clocking Design Guide for KeyStone Devices 2010/11/09
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010/11/09
Application note Optimizing Loops on the C66x DSP 2010/11/09
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010/11/09
User guide Flip Chip Ball Grid Array Package Reference Guide (Rev. A) 2005/05/23
Application note AN-1281 Bumped Die (Flip Chip) Packages (Rev. A) 2004/05/01

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TMDSEVM6657 — TMS320C6657 Lite 평가 모듈

The TMS3206657 Lite Evaluation Module (EVM), is an easy-to-use, cost-efficient development tool that helps developers quickly get started with designs using the C6657 or C6655 or C6654 family of DSPs. The EVM includes an on-board, single C6657 processor with robust connectivity options that allows (...)

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도터 카드

SHELD-3P-DSP-SOMS — Sheldon DSP-FPGA 보드

Sheldon Instruments designs and manufactures DSP based, COTS data acquisition and control hardware for PCIe/PCI, PCI104e/PCI104, XMC/PMC, and CompactPCI systems, along with drivers and real time development software for a variety of applications and markets.

Learn more about Sheldon Instruments at (...)
발송: Sheldon Instruments, Inc.
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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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소프트웨어 개발 키트(SDK)

BIOSMCSDK-C66X — SYS/BIOS MCSDK for C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
TMS320C6457 — 통신 인프라 디지털 신호 프로세서 TMS320C6657 — 고성능 듀얼 코어 C66x 고정 및 부동 소수점 DSP - 최대 1.25GHz, 2UART TMS320C6670 — 통신용 4코어 고정 및 부동 소수점 DSP TMS320C6678 — 고성능 옥토 코어 C66x 고정 및 부동 소수점 DSP - 최대 1.25GHz
다운로드 옵션
소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-C665X — C665x 프로세서용 프로세서 SDK - TI-RTOS 지원

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
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드라이버 또는 라이브러리

MATHLIB — 부동 소수점 디바이스용 DSP 수학 라이브러리

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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드라이버 또는 라이브러리

SPRC264 — TMS320C5000/6000 이미지 라이브러리(IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
사용 설명서: PDF
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드라이버 또는 라이브러리

SPRC265 — TMS320C6000 DSP 라이브러리(DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
사용 설명서: PDF
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드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

이 설계 리소스는 이러한 범주의 제품 대부분을 지원합니다.

제품 세부 정보 페이지에서 지원을 확인하십시오.
시작 다운로드 옵션
소프트웨어 코덱

C66XCODECS — 코덱 - 비디오, 음성 - C66x 기반 디바이스

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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소프트웨어 코덱

VOCAL-3P-DSPVOIPCODECS — Vocal technologies DSP VoIP 코덱

With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)
발송: VOCAL Technologies, Ltd.
파트너 사이트 방문
시뮬레이션 모델

C6657 Power Consumption Model

SPRM600.ZIP (178 KB) - Power Model
다운로드
시뮬레이션 모델

KeyStone I SerDes IBIS AMI Models

SPRM742.ZIP (969314 KB) - IBIS Model
lock = 수출 승인 필요(1분)
lock 다운로드
시뮬레이션 모델

TMS320C6655/57 CYP IBIS Model (revision 1.2)

SPRM570.ZIP (415 KB) - IBIS Model
다운로드
시뮬레이션 모델

TMS320C6657/55/54 CZH BSDL Model (Silicon Revision 1)

SPRM572.ZIP (21 KB) - BSDL Model
다운로드
회로도

TMS320C6655/57 ORCAD Capture Library Files

SPRR178.ZIP (12 KB)
다운로드
회로도

TMS320C6657 Thermal Model

SPRR183.ZIP (3 KB)
다운로드
레퍼런스 디자인

TIDEP-0099 — 음성 기반 애플리케이션을 위한 오디오 전처리 시스템 레퍼런스 디자인

This reference design uses multiple microphones, a beamforming algorithm, and other processes to extract clear speech and audio amidst noise and other clutter.  The rapid increase in applications that are used in noise-prone environments for voice activated digital assistants creates demand (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0045 — TI의 C6678 DSP에서 실시간 SAR(합성 개구면 레이더) 구현 레퍼런스 디자인

This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDEP0036 — 효율적인 OPUS 코덱 솔루션 구현을 위해 TMS320C6657을 사용한 레퍼런스 설계

The TIDEP0036 reference design provides an example of the ease of running TI optimized Opus encoder/decoder on the TMS320C6657 device. Since Opus supports a a wide range of bit rates, frame sizes and sampling rates, all with low delay, it has applicability for voice communications, networked audio (...)
Design guide: PDF
회로도: PDF
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCBGA (CZH) 625 Ultra Librarian
FCBGA (GZH) 625 Ultra Librarian
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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