封裝資訊
| 封裝 | 引腳 PDIP (N) | 16 |
| 作業溫度範圍 (°C) -55 to 125 |
| 包裝數量 | 運送包裝 25 | TUBE |
CD40175B 的特色
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Output compatible with two HTL loads, two low power TTL loads, or one low power Schottky TTL load
- Functional equivalent to TTL74175
- Standardized, symmetrical output characteristics
- Applications:
- Shift registers
- Buffer/storage registers
- Pattern generators
CD40175B 的說明
Cd40175B consists of four identical D-type flip-flops. Each flip-flop has an independent DATA D input and complementary Q and Q\ outputs. The CLOCK and CLEAR inputs are common to all flip-flops. Data are transferred to the Q outputs on the positive-going transition of the clock pulse. All four flip-flops are simultaneously reset by a low level on the CLEAR input.
These devices can function as shift register elements or as T-type flip-flops for toggle and counter applications.
The CD40175B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).