封裝資訊
| 封裝 | 引腳 PDIP (N) | 16 |
| 作業溫度範圍 (°C) -55 to 125 |
| 包裝數量 | 運送包裝 25 | TUBE |
CD4527B 的特色
- Cascadable in multiples of 4-bits
- Set to "9" input and "9" detect output
- 100% test for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100nA at 18V and 25°C
- Noise margin (full package-temperature range)=
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
- Applications
- Numerical control
- Instrumentation
- Digital filtering
- Frequency synthesis
CD4527B 的說明
CD4527B is a low-power 4-bit digital rate multiplier that provides an output-pulse rate which is the clock-input-pulse rate multiplied by 1/10 times the BCD input. For example, when the BCD input is 8, there will be 8 output pulses for every 10 input pulses. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversion, and frequency division.
For fractional multipliers with more than one digit, CD4527B devices may be cascaded in two different modes: the Add mode and the Multiply mode. (See Figs. 12 and 15). In the Add Mode,
| Output Rate = | ||
| (Clock Rate) | [0.1 BCD1 + 0.01 BCD2 + | 0.001 BCD3 + . . . ] |
In the Multiply mode, the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second one,
| 9 | 4 | 36 | ||||
| e.g. | — | × | — | = | — | or 36 output |
| 10 | 10 | 100 |
pulses for every 100 clock input pulses.
The CD4527B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).