產品詳細資料

Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 Supply current (max) (µA) 80 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) 0 to 70
Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Number of channels 8 IOL (max) (mA) 64 Supply current (max) (µA) 80 IOH (max) (mA) -15 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) 0 to 70
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 64-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP
  • BiCMOS Technology With Low Quiescent Power
  • Buffered Inputs
  • Noninverted Outputs
  • Input/Output Isolation From VCC
  • Controlled Output Edge Rates
  • 64-mA Output Sink Current
  • Output Voltage Swing Limited to 3.7 V
  • SCR Latch-Up-Resistant BiCMOS Process and Circuit Design
  • Package Options Include Plastic Small-Outline (M) and Shrink Small-Outline (SM) Packages and Standard Plastic (E) DIP

The CD74FCT541 is an octal buffer/driver with 3-state outputs that is ideal for driving bus lines or buffer memory address registers and uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA.

The 3-state control gate is a two-input AND gate with active-low inputs, so that if either output-enable (OE1\ or OE2\) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT541 is characterized for operation from 0°C to 70°C.

The CD74FCT541 is an octal buffer/driver with 3-state outputs that is ideal for driving bus lines or buffer memory address registers and uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 64 mA.

The 3-state control gate is a two-input AND gate with active-low inputs, so that if either output-enable (OE1\ or OE2\) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT541 is characterized for operation from 0°C to 70°C.

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類型 標題 日期
* Data sheet BiCMOS Octal Buffer/Driver With 3-State Outputs datasheet 2000年 7月 3日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日

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模擬型號

CD74FCT541 Behavioral SPICE Model

SCHM064.ZIP (7 KB) - PSpice Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian

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