CDC536
- Low-Output Skew for Clock-Distribution and Clock-Generation Applications
- Operates at 3.3-V VCC
- Distributes One Clock Input to Six Outputs
- One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
- No External RC Network Required
- External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
- Application for Synchronous DRAM, High-Speed Microprocessor
- Negative-Edge-Triggered Clear for Half-Frequency Outputs
- TTL-Compatible Inputs and Outputs
- Outputs Drive 50-
Parallel-Terminated Transmission Lines - State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
- Distributed VCC and Ground Pins Reduce Switching Noise
- Packaged in Plastic 28-Pin Shrink Small Outline Package
EPIC-IIB is a trademark of Texas Instruments.
The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock (CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clock.
Output-enable (OE)\ is provided for output control. When OE\ is high, the outputs are in the high-impedance state. When OE\ is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE\.
The CDC536 is characterized for operation from 0°C to 70°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDC536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet (Rev. G) | 2004年 7月 8日 | |
| Application note | Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers | 1996年 4月 1日 |
設計與開發
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|---|---|---|
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