ISO6760L
- ISO6760 with integrated Interlock function
- Designed to support opposite polarity of adjacent channels
- Three sets of paired interlock channels
- Robust isolation barrier:
- High lifetime at 1500 VRMS working voltage
- Up to 5000 VRMS isolation rating
- Up to 10 kV surge capability
- ±130 kV/µs typical CMTI
- Wide supply range: 1.71 V to 1.89 V and 2.25 V to 5.5 V
- Channel output non-inverting (ISO6760L) and inverting (ISO6760LN) options
- 50 Mbps data rate
- 1.71 V to 5.5 V level translation
- Wide temperature range: –40°C to 125°C
- 1.4 mA per channel typical at 1 Mbps
- Robust electromagnetic compatibility (EMC)
- System-level ESD, EFT, and surge immunity
- Low emissions
- Wide-SOIC (DW-16) Package
- Safety-Related Certifications:
- DIN EN IEC 60747-17 (VDE 0884-17)
- UL 1577 component recognition program
- IEC 62368-1, IEC 61010-1, IEC 60601-1 and GB 4943.1 certifications
The ISO6760L and ISO6760LN devices are high-performance, six-channel digital isolators with integrated interlock function for applications requiring up to 5000 VRMS isolation ratings per UL 1577. These devices are also certified by VDE, TUV, CSA, and CQC.
The ISO6760L family of devices integrate a series of logic gates to provide hardware interlock functionality for adjacent channels. The interlock feature ensures that each channel, in a channel pairing, will not be enabled at the same time. If both channels in the pairing share the same input logic, the output logic will always be low. The ISO6760L family of devices have all six channels in the same direction and provide high electromagnetic immunity and low emissions at low power consumption, while isolating CMOS or LVCMOS digital I/Os. Each isolation channel has a logic input and output buffer separated by TI’s double capacitive silicon dioxide (SiO2) insulation barrier.
Used in conjunction with intelligent power modules (IPMs), the interlock feature in these devices help prevent shoot through current between the high side and low side gate driver during turn on and turn off events. Six channels, including three pairings of interlock circuitry, are integrated in a 16-pin SOIC wide-body (DW) package with space savings greater than 50% compared to optocoupler solutions. Through innovative chip design and layout techniques, the electromagnetic compatibility of the ISO6760L devices has been significantly enhanced to ease system-level ESD, EFT, surge, and emissions compliance.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | ISO6760L Six-Channel Reinforced Digital Isolators with Integrated Interlock and Robust EMC datasheet (Rev. A) | PDF | HTML | 2023年 1月 3日 |
| Certificate | VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. S) | 2024年 2月 29日 | ||
| Certificate | CQC Certificate for ISOxxDWx (Rev. J) | 2023年 3月 27日 | ||
| Certificate | CSA Certificate for ISO676xDW (Rev. A) | 2023年 2月 15日 | ||
| Certificate | TUV Certificate for Isolation Devices (Rev. K) | 2022年 8月 5日 | ||
| Certificate | UL Certificate of Compliance File E181974 Vol 4 Sec 6 (Rev. P) | 2022年 8月 5日 | ||
| Functional safety information | ISO6760L/ISO6760L-Q1 Functional Safety FIT Rate, FMD and Pin FMA | PDF | HTML | 2022年 3月 10日 |
設計與開發
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DIGI-ISO-EVM — 通用數位隔離器評估模組
DIGI-ISO-EVM 是一款評估模組 (EVM)，可評估任何 TI 單通道、雙通道、三通道、四通道或六通道數位隔離器裝置，並提供五種不同封裝 - 8 接腳窄體 SOIC (D)、8 接腳寬體 SOIC (DWV)、16 接腳寬體 SOIC (DWW)、16 接腳超寬體 SOIC (DWW) 和 16 接腳 (DBQ) 封裝。EVM 具備足夠 Berg 接腳選項，可用於評估具最少外部零組件的裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (DW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。