ISOS141-SEP
- Radiation Tolerant
- Total Ionizing Dose (TID) Characterized (ELDRS-Free) = 30 krad(Si)
- TID RLAT/RHA = 30 krad(Si)
- Single-Event Latch-up (SEL) Immune to LET = 43 MeV⋅cm2/mg at 125°C
- Single-Event Dielectric Rupture (SEDR) Immune (43 MeV⋅cm2/mg) at 500 VDC
- Space Enhanced Plastic (Space EP)
- Meets NASA’s ASTM E595 Outgassing Spec
- Vendor Item Drawing (VID) V62/21610
- Military Temp Range (-55°C to 125°C)
- One Wafer Fabrication Site
- One Assembly and Test Site
- Gold Bond Wire, NiPdAu Lead Finish
- Wafer Lot Traceability
- Extended Product Life Cycle
- Extended Product Change Notification
- 600 VRMS continous working voltage
- Section 6.7:
- DIN VDE V 0884-11:2017-01
- UL 1577 component recognition program
- 100 Mbps data rate
- Wide supply range: 2.25 V to 5.5 V
- 2.25-V to 5.5-V level translation
- Default output low
- Low power consumption, 1.5 mA per channel typical at 1 Mbps
- Low propagation delay: 10.7 ns typical (5-V Supplies)
- Low channel-to-channel skew: 4 ns max (5-V Supplies)
- ±100 kV/µs typical CMTI
- System-level ESD, EFT, Surge, and Magnetic Immunity
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Small QSOP (DBQ-16) package
The ISOS141-SEP radiation-tolerant device is a high-performance, quad-channel digital isolator in a small form factor 16-pin QSOP package. Each isolation channel has a logic input and output buffer separated by a double capacitive silicon dioxide (SiO2) insulation barrier. This device supports low Earth orbit (LEO) space applications with its high data rate of 100 Mbps, low propagation delay of 10.7 ns, and tight channel-to-channel skew of 4 ns. The ISOS141-SEP device has three forward and one reverse-direction channels and if the input power or signal is lost, the default output is low. The enable pins can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption.
The ISOS141-SEP provides high electromagnetic immunity and low emissions with low power consumption, while isolating CMOS or LVCMOS digital I/Os. The device has a high common-mode transient immunity of 100 kV/µs and can ease system-level ESD, EFT, surge, and simplify emissions compliance through its innovative chip design.
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DBQ) | 16 | Ultra Librarian |
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