SN5476

現行

具有預設和清除功能的二路 J-K 正反器

立即訂購

產品規格表

document-pdfAcrobat Dual J-K Flip-Flops With Preset And Clear datasheet (英文)

SN5476

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

2

Technology family

TTL

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL

IOL (max) (mA)

-0.4

IOH (max) (mA)

16

Operating temperature range (°C)

-55 to 125

Rating

Military

Number of channels

2

Technology family

TTL

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Input type

TTL

IOL (max) (mA)

-0.4

IOH (max) (mA)

16

Operating temperature range (°C)

-55 to 125

Rating

Military

CDIP (J)

16

135.3552 mm² 19.56 x 6.92

CFP (W)

16

69.319 mm² 10.3 x 6.73

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages
Dependable Texas Instruments Quality and Reliability

Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages
Dependable Texas Instruments Quality and Reliability

The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.

The SN5476 and the SN54LS76A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7476 and the SN74LS76A are characterized for operation from 0°C to 70°C.

The '76 contains two independent J-K flip-flops with individual J-K, clock, preset, and clear inputs. The '76 is a positive-edge-triggered flip-flop. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS76A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. The preset and clear are asynchronous active low inputs. When low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table.

The SN5476 and the SN54LS76A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7476 and the SN74LS76A are characterized for operation from 0°C to 70°C.

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