產品詳細資料

Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 48 IOH (max) (mA) -16 Supply current (max) (µA) 100 Input type TTL-Compatible CMOS Output type 3-State Features High speed (tpd 10-50ns), Input clamp diode Rating Military Operating temperature range (°C) -55 to 125
Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 48 IOH (max) (mA) -16 Supply current (max) (µA) 100 Input type TTL-Compatible CMOS Output type 3-State Features High speed (tpd 10-50ns), Input clamp diode Rating Military Operating temperature range (°C) -55 to 125
CDIP (JT) 28 269.5956 mm² 36.83 x 7.32 LCCC (FK) 28 130.6449 mm² 11.43 x 11.43
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Serial Test Bus
  • Allow Partitioning of System Scan Paths
  • Can Be Cascaded Horizontally or Vertically
  • Select Up to Four Secondary Scan Paths to Be Included in a Primary Scan Path
  • Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals
  • Include 4-Bit Identification Bus for Scan-Path Identification
  • Inputs Are TTL Compatible
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Serial Test Bus
  • Allow Partitioning of System Scan Paths
  • Can Be Cascaded Horizontally or Vertically
  • Select Up to Four Secondary Scan Paths to Be Included in a Primary Scan Path
  • Include 8-Bit Programmable Binary Counter to Count or Initiate Interrupt Signals
  • Include 4-Bit Identification Bus for Scan-Path Identification
  • Inputs Are TTL Compatible
  • EPICTM (Enhanced-Performance Implanted CMOS) 1-m Process
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

 

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

The 'ACT8997 are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.

The 'ACT8997 enhance the scan capability of TI's SCOPETM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.

By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.

All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.

The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.

The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.

The 'ACT8997 are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of components facilitates testing of complex circuit-board assemblies.

The 'ACT8997 enhance the scan capability of TI's SCOPETM family by allowing augmentation of a system's primary scan path with secondary scan paths (SSPs), which can be individually selected by the 'ACT8997 for inclusion in the primary scan path. These devices also provide buffering of test signals to reduce the need for external logic.

By loading the proper values into the instruction register and data registers, the user can select up to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any of the device's six data registers or the instruction register can be placed in the device's scan path, i.e., placed between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.

All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on either the rising or falling edge of DCI.

The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.

The SN54ACT8997 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8997 is characterized for operation from 0°C to 70°C.

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類型 標題 日期
* Data sheet Scan Path Linkers With 4-Bit Identification Buses Scan-Controlled IEEE Std datasheet (Rev. D) 1996年 12月 1日
* SMD SN54ACT8997 SMD 5962-93239 2016年 6月 21日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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CDIP (JT) 28 Ultra Librarian
LCCC (FK) 28 Ultra Librarian

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