SN54ALS243A
- Two-Way Asynchronous Communication Between Data Buses
- pnp Inputs Reduce dc Loading
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These quadruple bus transceivers are designed for asynchronous
two-way communication between data buses. The control-function
implementation allows for maximum flexibility in timing. These
devices allow data transmission from the A bus to the B bus or from
the B bus to the A bus depending upon the logic levels at the
output-enable (OEBA and 
)
inputs. The output-enable inputs can be used to disable the device so
that the buses are effectively isolated.
The dual-enable configuration gives the quadruple bus transceivers
the capability to store data by simultaneously enabling OEBA and . Each output reinforces its input
in this transceiver configuration. When both control inputs are
enabled and all other data sources to the two sets of bus lines are
at high impedance, both sets of bus lines (eight in all) retain their
states. The 4-bit codes appearing on the two sets of buses are
identical.
The SN54ALS243A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS243A is characterized for operation from 0°C to 70°C.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Quadruple Bus Transceivers With 3-State Outputs datasheet (Rev. B) | 1994年 12月 1日 | |
| * | SMD | SN54ALS243A SMD 84013022A | 2016年 6月 21日 | |
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
| Application note | Live Insertion | 1996年 10月 1日 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 1995年 8月 1日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LCCC (FK) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點