SN54BCT623
- State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
- ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Plastic and Ceramic 300-mil DIPs (J, N)
The ´BCT623 bus transceiver is designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. The ´BCT623 provides true data at its outputs.
This device allows data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic levels at the
output-enable (OEAB and 
)
inputs.
The output-enable inputs can be used to disable the device so that
the buses are effectively isolated. The dual-enable configuration
gives the transceivers the capability of storing data by
simultaneously enabling OEAB and . Each output reinforces its input in this
configuration. When both OEAB and are enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus lines (16 in
all) will remain at their last states.
The SN54BCT623 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT623 is characterized for operation from 0°C to 70°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Octal Bus Transceivers With 3-State Outputs datasheet (Rev. A) | 1993年 11月 1日 | |
| * | SMD | SN54BCT623 SMD 5962-90940 | 2016年 6月 21日 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
| Application note | Live Insertion | 1996年 10月 1日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CDIP (J) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點