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SN54SC6T14-SEP

現行

具施密特觸發器輸入的耐輻射六位元反相固定方向位準轉換器

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產品規格表

SN54SC6T14-SEP

現行
產品規格表 立即訂購

產品詳細資料

Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type Push-Pull Rating Space Operating temperature range (°C) -55 to 125
Technology family SCxT Vout (min) (V) 1.2 Vout (max) (V) 5.5 Features Balanced outputs, Over-voltage tolerant inputs Input type TTL-Compatible CMOS Output type Push-Pull Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² 5 x 6.4
  • Vendor item drawing available, VID V62/24618
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25 mA AT 5V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/24618
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25 mA AT 5V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC6T14-SEP device contains six independent Inverters with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).

The SN54SC6T14-SEP device contains six independent Inverters with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).
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類型 標題 日期
* Data sheet SN54SC6T14-SEP Radiation Tolerant, Hex Schmitt-Trigger Inverters With Integrated Translation datasheet PDF | HTML 2023年 1月 20日
* Radiation & reliability report SN54SC6T14-SEP Production Flow and Reliability Report PDF | HTML 2024年 4月 10日
* Radiation & reliability report SN54SC6T07-SEP Single Event Effects Radiation Report PDF | HTML 2024年 2月 21日
* Radiation & reliability report SN54SC6T14-SEP Total Ionizing Dose (TID) Radiation Report PDF | HTML 2024年 2月 12日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024年 9月 10日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日

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