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非反相緩衝器和驅動器

SN74ABT16825

現行

具有 TTL 相容 CMOS 輸入和 3 態輸出的 18 通道、4.5-V 至 5.5-V 緩衝器

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產品規格表

SN74ABT16825

現行
產品規格表 立即訂購

產品詳細資料

Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 Supply current (max) (µA) 32000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ABT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 Supply current (max) (µA) 32000 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35
  • Members of Texas Instruments' WidebusTM Family
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
  • Typical VOLP (Output Ground Bounce)
    <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)

Widebus is a trademark of Texas Instruments.
  • Members of Texas Instruments' WidebusTM Family
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD 17
  • Typical VOLP (Output Ground Bounce)
    <1 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)

Widebus is a trademark of Texas Instruments.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The 'ABT16825 devices are 18-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices can be used as two 9-bit buffers or one 18-bit buffer. They provide true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技術文件

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類型 標題 日期
* Data sheet 18-Bit Buffers/Drivers 18-Bit Buffers/Drivers With 3-State Outputs datasheet (Rev. D) 2000年 10月 3日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 2004年 2月 16日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 1997年 3月 1日
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ABT16825 Behavioral SPICE Model

SCBM148.ZIP (7 KB) - PSpice Model
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SSOP (DL) 56 Ultra Librarian
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