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SN74AHC125-EP

現行

具 3 態輸出的強化型產品 4 通道、2-V 至 5.5-V 緩衝器

立即訂購
產品規格表

SN74AHC125-EP

現行
產品規格表 立即訂購

產品詳細資料

Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 50 Supply current (max) (µA) 40 IOH (max) (mA) -50 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
Technology family AHC Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 50 Supply current (max) (µA) 40 IOH (max) (mA) -50 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 150 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 1000 V Per MIL-STD-833, Method 3015; Exceeds 150 V Using Machine Model (C = 200 pF, R = 0)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

EPIC is a trademark of Texas Instruments.

The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high. When OE\ is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AHC125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high. When OE\ is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 日期
* Data sheet SN74AHC125-EP datasheet (Rev. A) 2003年 5月 30日
* VID SN74AHC125-EP VID V6203648 2016年 6月 21日
* Radiation & reliability report SN74AHC125MDREP Reliability Report 2016年 4月 11日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 2002年 12月 2日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 2000年 2月 24日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 1998年 4月 1日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Live Insertion 1996年 10月 1日

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
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