封裝資訊
| 封裝 | 針腳 SOIC (D) | 14 |
| 操作溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送業者 2,500 | LARGE T&R |
SN74AHCT125 的特色
- Inputs are TTL-voltage compatible
- Latch-up performance exceeds 250mA per JESD 17
SN74AHCT125 的說明
The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
For the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.