SN74ALS541
- 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
- pnp Inputs Reduce dc Loading
- Data Flowthrough Pinout (All Inputs on Opposite Side From Outputs)
These octal buffers and line drivers are designed to have the performance of the popular SN54ALS240A/ SN74ALS240A series and, at the same time, offer a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.
The 3-state control gate is a 2-input NOR gate such that, if either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state.
The SN74ALS540 provides inverted data. The ’ALS541 provide true data at the outputs.
The –1 versions of SN74ALS540 and SN74ALS541 are identical to the standard versions, except that the recommended maximum IOL is increased to 48 mA. There is no –1 version of the SN54ALS541.
您可能會感興趣的類似產品
引腳對引腳且具備與所比較裝置相同的功能
技術文件
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (N) | 20 | Ultra Librarian |
SOIC (DW) | 20 | Ultra Librarian |
SOP (NS) | 20 | Ultra Librarian |
SSOP (DB) | 20 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點