SN74ALVC126

Name: SN74ALVC126
Brand: TI
SKU: SN74ALVC126
Price: 0.349 USD

現行

具有 3 態輸出的 4 通道 1.65-V 至 3.6-V 緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74ALVC126 datasheet (Rev. J) (英文)

SN74ALVC126

現行

產品規格表

立即訂購

產品詳細資料

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ALVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

3.6

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-24

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

51.9 mm² 8.65 x 6

79.56 mm² 10.2 x 7.8

32 mm² 5 x 6.4

23.04 mm² 3.6 x 6.4

Operates From 1.65 V to 3.6 V
Max t_pd of 3.1 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.1 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

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SN74LVC125A

現行

具有 3 態輸出的四通道 1.65V 至 3.6V 緩衝器 Larger voltage range (1.65V to 5.5V)

功能與所比較的裝置相似

SN74LVC126A

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具有三態輸出的四通道、1.65V 至 3.6V 緩衝器 Larger voltage range (1.65V to 5.5V)

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	類型	標題	日期
*	Data sheet	SN74ALVC126 datasheet (Rev. J)	2004年 9月 17日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	User guide	ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)	2002年 8月 1日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	2002年 6月 13日
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	2002年 5月 22日
	Application note	Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)	1999年 9月 8日
	Application note	TI SN74ALVC16835 Component Specification Analysis for PC100	1998年 8月 3日
	Application note	Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)	1998年 5月 13日
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	1997年 12月 1日
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	1997年 8月 1日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	Input and Output Characteristics of Digital Integrated Circuits	1996年 10月 1日
	Application note	Live Insertion	1996年 10月 1日
	Application note	Understanding Advanced Bus-Interface Products Design Guide	1996年 5月 1日