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SN74ALVC162836

現行

具有 3 態輸出的 20 位元通用匯流排驅動器

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產品規格表

SN74ALVC162836

現行
產品規格表 立即訂購

產品詳細資料

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type Standard CMOS Output type 3-State Features Balanced outputs, Damping resistors, Over-voltage tolerant inputs, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 4 ns at 3.3 V
  • ±12-mA Output Drive at 3.3 V
  • Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.
  • Member of the Texas Instruments Widebus™ Family
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 4 ns at 3.3 V
  • ±12-mA Output Drive at 3.3 V
  • Output Port Has Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.

This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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類型 標題 日期
* Data sheet SN74ALVC162836 datasheet (Rev. E) 2004年 8月 24日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ALVC162836 IBIS Model (Rev. B)

SCEM031B.ZIP (46 KB) - IBIS Model
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SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian
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