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SN74ALVCH162601

現行

具有 3 態輸出的 18 位元通用匯流排收發器

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產品規格表

SN74ALVCH162601

現行
產品規格表 立即訂購

產品詳細資料

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Positive input clamp diode, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 12 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Positive input clamp diode, Ultra high speed (tpd <5ns) Technology family ALVC Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
  • B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR.

Widebus, EPIC, UBT are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
  • B-Port Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

NOTE: For tape-and-reel order entry, the DGGR package is abbreviated to GR.

Widebus, EPIC, UBT are trademarks of Texas Instruments.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.

The B-port outputs include equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162601 is characterized for operation from –0°C to 85°C.

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.

The B-port outputs include equivalent 26- series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162601 is characterized for operation from –0°C to 85°C.
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類型 標題 日期
* Data sheet SN74ALVCH162601 datasheet (Rev. H) 2004年 8月 16日
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ALVCH162601 IBIS Model

SCEM277.ZIP (105 KB) - IBIS Model
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SSOP (DL) 56 Ultra Librarian
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