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SN74ALVCH16825

現行

具匯流排電位保持和 3 態輸出的 18 通道、1.65-V 至 3.6-V 緩衝器

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產品規格表

SN74ALVCH16825

現行
產品規格表 立即訂購

產品詳細資料

Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 18 IOL (max) (mA) 24 Supply current (max) (µA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus™ Family
  • EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

This 18-bit buffer and line driver is designed for 1.65-V to 3.6-V VCC operation.

This SN74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as two 9-bit buffers or one 18-bit buffer. It provides true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.

The SN74ALVCH16825 is characterized for operation from &$150;40°C to 85°C.

This 18-bit buffer and line driver is designed for 1.65-V to 3.6-V VCC operation.

This SN74ALVCH16825 improves the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as two 9-bit buffers or one 18-bit buffer. It provides true data.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all nine affected outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.

The SN74ALVCH16825 is characterized for operation from &$150;40°C to 85°C.
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類型 標題 日期
* Data sheet SN74ALVCH16825 datasheet (Rev. D) 2004年 9月 2日
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
User guide ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
Application note TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
Application note Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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模擬型號

SN74ALVCH16825 Behavioral SPICE Model

SCEM753.ZIP (7 KB) - PSpice Model
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SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
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