SN74AUC1G126

Name: SN74AUC1G126
Brand: TI
SKU: SN74AUC1G126
Price: 0.06 USD

現行

具有 3 態輸出的單路 0.8-V 至 2.7-V 高速緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output datasheet (Rev. L) (英文) PDF | HTML

SN74AUC1G126

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AUC

Supply voltage (min) (V)

0.8

Supply voltage (max) (V)

2.7

Number of channels

1

IOL (max) (mA)

9

Supply current (max) (µA)

10

IOH (max) (mA)

-9

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

DSBGA (YZP)

5

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in TI’s NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial Power Down Mode and Back Drive Protection
Sub-1 V Operable
Maximum t_pd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Available in TI’s NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
I_off Supports Partial Power Down Mode and Back Drive Protection
Sub-1 V Operable
Maximum t_pd of 2.5 ns at 1.8 V
Low Power Consumption, 10-µA Maximum I_CC
±8-mA Output Drive at 1.8 V

The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.

The SN74AUC1G126 bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G126 device is a single line driver with a tri-state output. The output is disabled when the output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoFree™ package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, which prevents damaging current backflow through the device when it is powered down.

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	類型	標題		日期
*	Data sheet	SN74AUC1G126 Single Bus Buffer Gate With Tri-state Output datasheet (Rev. L)	PDF \| HTML	2018年 1月 5日
	Selection guide	Little Logic Guide 2018 (Rev. G)		2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)		2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)		2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)		2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)		2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)		2003年 11月 14日
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices		2003年 3月 21日
	User guide	AUC Data Book, January 2003 (Rev. A)		2003年 1月 1日
	Application note	Texas Instruments Little Logic Application Report		2002年 11月 1日
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	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		2002年 6月 13日
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	More literature	AUC Product Brochure (Rev. A)		2002年 3月 18日