產品詳細資料

Technology family AUP1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.6 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -6 IOL (max) (mA) -6 Supply current (max) (µA) 3.6 Features 1, 1.45, 4.2 Input type Schmitt-Trigger, Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AUP1T Applications GPIO Bits (#) 1 Configuration 1 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.6 High input voltage (max) (V) 3.6 Vout (min) (V) 0 Vout (max) (V) 3.6 Data rate (max) (Mbps) 200 IOH (max) (mA) -6 IOL (max) (mA) -6 Supply current (max) (µA) 3.6 Features 1, 1.45, 4.2 Input type Schmitt-Trigger, Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Balanced Propagation Delays: tPLH = tPHL (1.8-V to 3.3-V Translation Typical)
  • Low Static-Power Consumption: Maximum of 5-µA ICC
  • ±6-mA Output Drive at 3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • VCC Isolation Feature – If VCCA Input Is at GND, B Port Is in the High-Impedance state
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • ESD Protection Exceeds JESD 22
  • 5000-V Human-Body Model (A114-A)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Balanced Propagation Delays: tPLH = tPHL (1.8-V to 3.3-V Translation Typical)
  • Low Static-Power Consumption: Maximum of 5-µA ICC
  • ±6-mA Output Drive at 3 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • VCC Isolation Feature – If VCCA Input Is at GND, B Port Is in the High-Impedance state
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • ESD Protection Exceeds JESD 22
  • 5000-V Human-Body Model (A114-A)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The SN74AUP1T34 device is a 1-bit noninverting translator that uses two separate configurable power-supply rails. It is a uni-directional translator from A to B. The A port is designed to track VCCA. VCCA accepts supply voltages from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts supply voltages from 0.9 V to 3.6 V. This allows for low-voltage translation between 1-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AUP1T34 is also fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if VCCA input is at GND, the B port is in the high-impedance state. If VCCB input is at GND, any input to the A side does not cause the leakage current even floating.

The SN74AUP1T34 device is a 1-bit noninverting translator that uses two separate configurable power-supply rails. It is a uni-directional translator from A to B. The A port is designed to track VCCA. VCCA accepts supply voltages from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts supply voltages from 0.9 V to 3.6 V. This allows for low-voltage translation between 1-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AUP1T34 is also fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if VCCA input is at GND, the B port is in the high-impedance state. If VCCB input is at GND, any input to the A side does not cause the leakage current even floating.

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類型 標題 日期
* Data sheet SN74AUP1T34 1-Bit Unidirectional Voltage-Level Translator datasheet (Rev. F) PDF | HTML 2018年 4月 20日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日

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SN74AUP1T34 IBIS Model

SCEM554.ZIP (43 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian

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