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SN74AVC16245

現行

具有 3 態輸出的 16 位元匯流排收發器

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產品規格表

SN74AVC16245

現行
產品規格表 立即訂購

產品詳細資料

Supply voltage (min) (V) 1.2 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type CMOS Output type CMOS Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AVC Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 1.2 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type CMOS Output type CMOS Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Technology family AVC Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Latch-Up Performance Exceeds 250 mA Per JESD 78
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

    DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
  • Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC
  • Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Latch-Up Performance Exceeds 250 mA Per JESD 78
  • Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

    DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16245 is characterized for operation from -40°C to 85°C.

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.

This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.

The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74AVC16245 is characterized for operation from -40°C to 85°C.
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SN74LVTH16245A 現行 具有 3 態輸出的 3.3-V ABT 16 位元匯流排收發器 Voltage range 2.7V to 3.6V, average propagation delay 4.5ns, average drive strength 64mA

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類型 標題 日期
* Data sheet 16-Bit Bus Transceiver With 3-State Outputs datasheet (Rev. L) 2000年 2月 21日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

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模擬型號

HSPICE MODEL OF SN74AVC16245

SCEJ196.ZIP (95 KB) - HSpice Model
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模擬型號

SN74AVC16245 IBIS Model

SCEM403.ZIP (69 KB) - IBIS Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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