SN74AVC20T245

Name: SN74AVC20T245
Brand: TI
SKU: SN74AVC20T245
Price: 1.231 USD

現行

具有可配置電壓轉換和 3 態輸出的 20 位元雙電源供電匯流排收發器

立即訂購

產品規格表

document-pdfAcrobat SN74AVC20T245 20-Bit Dual-Supply Bus Transceiver datasheet (Rev. F) (英文)

SN74AVC20T245

現行

產品規格表

立即訂購

產品詳細資料

Technology family

AVC

Bits (#)

20

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3

Data rate (max) (Mbps)

380

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

65

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

AVC

Bits (#)

20

High input voltage (min) (V)

0.78

High input voltage (max) (V)

3.6

Vout (min) (V)

1.2

Vout (max) (V)

3

Data rate (max) (Mbps)

380

IOH (max) (mA)

-12

IOL (max) (mA)

12

Supply current (max) (µA)

65

Features

Output enable, Overvoltage tolerant inputs, Partial power down (Ioff)

Input type

Standard CMOS

Output type

3-State, Balanced CMOS, Push-Pull

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (DGG)

56

113.4 mm² 14 x 8.1

TVSOP (DGV)

56

72.32 mm² 11.3 x 6.4

Control Inputs V_IH/V_IL Levels are Referenced to V_CCA Voltage
V_CC Isolation Feature - If Either V_CC Input Is at GND, Both Ports Are in the High-Impedance State
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
I_off Supports Partial-Power-Down Mode Operation
I/Os Are 4.6-V Tolerant
Max Data Rates
- 380 Mbps (1.8-V to 3.3-V Translation)
- 260 Mbps (1.8-V to 3.3-V Translation)
- 260 Mbps (Translate to 2.5 V)
- 210 Mbps (Translate to 1.8 V)
- 120 Mbps (Translate to 1.5 V)
- 100 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Control Inputs V_IH/V_IL Levels are Referenced to V_CCA Voltage
V_CC Isolation Feature - If Either V_CC Input Is at GND, Both Ports Are in the High-Impedance State
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
I_off Supports Partial-Power-Down Mode Operation
I/Os Are 4.6-V Tolerant
Max Data Rates
- 380 Mbps (1.8-V to 3.3-V Translation)
- 260 Mbps (1.8-V to 3.3-V Translation)
- 260 Mbps (Translate to 2.5 V)
- 210 Mbps (Translate to 1.8 V)
- 120 Mbps (Translate to 1.5 V)
- 100 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 8000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This 20-bit noninverting bus transceiver uses two separate configurable power-supply rails.

The SN74AVC20T245 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC20T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so that the buses are effectively isolated.

The SN74AVC20T245 is designed so that the control (1DIR, 2DIR, 1OE\, and 2OE\) inputs are supplied by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 20-bit noninverting bus transceiver uses two separate configurable power-supply rails.

The SN74AVC20T245 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC20T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the outputs so that the buses are effectively isolated.

The SN74AVC20T245 is designed so that the control (1DIR, 2DIR, 1OE\, and 2OE\) inputs are supplied by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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	類型	標題		日期
*	Data sheet	SN74AVC20T245 20-Bit Dual-Supply Bus Transceiver datasheet (Rev. F)		2005年 4月 19日
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