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邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74AVC32T245

現行

具有可配置電壓轉換和 3 態輸出的 32 位元雙電源供電匯流排收發器

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產品規格表

SN74AVC32T245

現行
產品規格表 立即訂購

產品詳細資料

Technology family AVC Bits (#) 32 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 90 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 32 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 90 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NMJ) 96 74.25 mm² 13.5 x 5.5
  • Member of the Texas Instruments Widebus+™ Family
  • Control Inputs VIH/VIL Levels Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2 V to 3.6 V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • 4.6 V Tolerant I/Os
  • Max Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (< 1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000 V Human-Body Model (A114-A)
    • 1000 V Charged-Device Model (C101)
  • Member of the Texas Instruments Widebus+™ Family
  • Control Inputs VIH/VIL Levels Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2 V to 3.6 V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • 4.6 V Tolerant I/Os
  • Max Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (< 1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000 V Human-Body Model (A114-A)
    • 1000 V Charged-Device Model (C101)

This 32-bit noninverting bus transceiver uses two separate, configurable power-supply rails. The SN74AVC32T245 device is optimized to operate with VCCA/VCCB set from 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC32T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can disable the outputs so the buses are effectively isolated.

The SN74AVC32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1 OE, 2 OE, 3 OE, and 4 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 32-bit noninverting bus transceiver uses two separate, configurable power-supply rails. The SN74AVC32T245 device is optimized to operate with VCCA/VCCB set from 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC32T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can disable the outputs so the buses are effectively isolated.

The SN74AVC32T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 1 OE, 2 OE, 3 OE, and 4 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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技術文件

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類型 標題 日期
* Data sheet SN74AVC32T245 32-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation, Level-Shifting, and Tri-State Outputs datasheet (Rev. H) PDF | HTML 2020年 11月 11日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

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模擬型號

SN74AVC32T245 IBIS Model

SCEM462.ZIP (69 KB) - IBIS Model
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參考設計

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Design guide: PDF
電路圖: PDF
參考設計

TIDEP0047 — 採用 TI AM57x 處理器參考設計的電源和熱能設計考量

This is a reference design based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and TPS659037.  It includes (...)
Design guide: PDF
電路圖: PDF
參考設計

DLP4500-C350REF — 採用 DLP 技術的高解析度、可攜式光源操控參考設計

This reference design, featuring the DLP® 0.45” WXGA chipset and implemented in the DLP® LightCrafter™ 4500 evaluation module (EVM), enables flexible control of high resolution, accurate patterns for industrial, medical, and scientific applications. With a free USB-based GUI and (...)
Test report: PDF
電路圖: PDF
參考設計

TIDA-00254 — 使用 DLP® 技術且適用於 3D 機器視覺應用的精確點雲產生

The 3D Machine Vision reference design employs Texas Instruments DLP® Advanced Light Control Software Development Kit (SDK) for LightCrafter™ series controllers, which allows developers to easily construct 3D point clouds by integrating TI’s digital micromirror device (DMD) (...)
Test report: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (NMJ) 96 Ultra Librarian
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  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
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  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
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