首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 方向控制電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74AVC4T774

現行

具有可配置電平移位變化和三態輸出的四位元雙電源匯流排收發器

立即訂購
產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
可直接投入的替代產品，相較於所比較的裝置，具備升級功能
SN74AXC4T774 現行 具有三態輸出和獨立方向控制輸入的 4 位元雙電源匯流排收發器 Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVC4T774

現行
產品規格表 立即訂購

產品詳細資料

Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23-THN (DYY) 16 8.4 mm² 4.2 x 2 TSSOP (PW) 16 32 mm² 5 x 6.4 UQFN (RSV) 16 4.68 mm² 2.6 x 1.8 VQFN (RGY) 16 14 mm² 4 x 3.5 WQFN (BQB) 16 8.75 mm² 3.5 x 2.5
  • Each channel has an independent DIR control input
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.1V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff Supports partial power-down-mode operation
  • Typical data rates
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD Protection exceeds the following levels (tested per JESD 22)
    • ±8000V Human-body model (A114-A)
    • 250V Machine model (A115-A)
    • ±1500V Charged-device model (C101)
  • Each channel has an independent DIR control input
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.1V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff Supports partial power-down-mode operation
  • Typical data rates
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD Protection exceeds the following levels (tested per JESD 22)
    • ±8000V Human-body model (A114-A)
    • 250V Machine model (A115-A)
    • ±1500V Charged-device model (C101)

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1 V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bi-directional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

For a high-impedance state during power-up or power-down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low-GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (for example, capacitance, board-layout, package inductance, surrounding conditions, and so forth), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current.

This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.1 V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.1 to 3.6V. The SN74AVC4T774 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bi-directional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T774 is designed for asynchronous communication between data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports in the high-impedance mode. The device transmits data from the A bus to the B bus when the B outputs are activated, and from the B bus to the A bus when the A outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T774 is designed so that the control pins (DIR1, DIR2, DIR3, DIR4, and OE) are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

For a high-impedance state during power-up or power-down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Since this device has CMOS inputs, it is very important to not allow them to float. If the inputs are not driven to either a high VCC state, or a low-GND state, an undesirable larger than expected ICC current may result. Since the input voltage settlement is governed by many factors (for example, capacitance, board-layout, package inductance, surrounding conditions, and so forth), ensuring that they these inputs are kept out of erroneous switching states and tying them to either a high or a low level minimizes the leakage-current.
filter 尋找其它 方向控制電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 20
類型 標題 日期
* Data sheet SN74AVC4T774 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage-Level datasheet (Rev. H) 2024年 3月 18日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Application note Optimizing Video Doorbell Designs with Common Logic Use Cases (Rev. A) PDF | HTML 2021年 4月 1日
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML 2021年 3月 29日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
White paper Solving CMOS Transition Rate Issues Using Schmitt Trigger Solution (Rev. A) 2017年 5月 1日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015年 4月 30日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
More literature LCD Module Interface Application Clip 2003年 5月 9日
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002年 8月 20日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999年 7月 7日
Application note AVC Logic Family Technology and Applications (Rev. A) 1998年 8月 26日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
TI.com 無法提供
開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

使用指南: PDF
TI.com 無法提供
模擬型號

IBIS Model for SN74AVC4T774

SCEM539.ZIP (63 KB) - IBIS Model
下載

許多 TI 參考設計包含 SN74AVC4T774

使用我們的參考設計選擇工具，以檢視並找出最適合您的應用和參數的設計。

檢視參考設計
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOT-23-THN (DYY) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
UQFN (RSV) 16 Ultra Librarian
VQFN (RGY) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片