SN74HCS74-Q1

現行

具有清除與預設功能的汽車施密特觸發輸入雙 D 型正緣觸發正反器

產品詳細資料

Number of channels 2 Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 45 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Automotive
Number of channels 2 Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Schmitt-Trigger Output type Push-Pull Clock frequency (max) (MHz) 45 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Supply current (max) (µA) 2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -40 to 125 Rating Automotive
SOIC (D) 14 51.9 mm² 8.65 x 6 SOT-23-THN (DYY) 14 13.692 mm² 4.2 x 3.26 TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, TA
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classifcation Level C6
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V
  • AEC-Q100 Qualified for automotive applications:
    • Device temperature grade 1: –40°C to +125°C, TA
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classifcation Level C6
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 6 V

The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset ( PRE) input sets the output high. A low level at the clear ( CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q).

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類型 標題 日期
* Data sheet SN74HCS74-Q1 Automotive Schmitt-Trigger Input Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset datasheet (Rev. E) PDF | HTML 2021年 12月 7日
EVM User's guide 14-24-Logic-EVM User's Guide (Rev. B) PDF | HTML 2022年 9月 6日
Functional safety information SN74HCS74-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA PDF | HTML 2021年 3月 11日
Application note Reduce Noise and Save Power with the New HCS Logic Family (Rev. A) 2020年 4月 20日

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開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM),設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
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模擬型號

SN74HCS74-Q1 IBIS Model (Rev. A)

SCEM590A.ZIP (51 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 14 Ultra Librarian
SOT-23-THN (DYY) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian

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  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
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