SN74LV126A

Name: SN74LV126A
Brand: TI
SKU: SN74LV126A
Price: 0.072 USD

現行

具有 3 態輸出的 4 通道 2-V 至 5.5-V 緩衝器

立即訂購

產品規格表

document-pdfAcrobat SN74LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. J) (英文) PDF | HTML

SN74LV126A

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

Supply current (max) (µA)

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

51.9 mm² 8.65 x 6

79.56 mm² 10.2 x 7.8

48.36 mm² 6.2 x 7.8

32 mm² 5 x 6.4

23.04 mm² 3.6 x 6.4

2V to 5.5V VCC operation
Maximum tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Ioff supports live insertion, partial power down mode, and back drive protection
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mAper JESD 17

2V to 5.5V VCC operation
Maximum tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Ioff supports live insertion, partial power down mode, and back drive protection
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mAper JESD 17

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

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