封裝資訊
封裝 | 針腳 SOIC (D) | 14 |
操作溫度範圍 (°C) -40 to 125 |
包裝數量 | 運送業者 2,500 | LARGE T&R |
SN74LV126A 的特色
- 2V to 5.5V VCC operation
- Maximum tpd of 6.5ns at 5V
- Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
- Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
- Ioff supports live insertion, partial power down mode, and back drive protection
- Support mixed-mode voltage operation on all ports
- Latch-up performance exceeds 250mAper JESD 17
SN74LV126A 的說明
The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.