SN74LV240A

Name: SN74LV240A
Brand: TI
SKU: SN74LV240A
Price: 0.115 USD

現行

具有 3 態輸出的 8 通道 2V 至 5.5V 逆變器

立即訂購

產品規格表

document-pdfAcrobat SN74LV240A Octal Inverting Buffers/Drivers With 3-State Outputs datasheet (Rev. K) (英文) PDF | HTML

SN74LV240A

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-16

Supply current (max) (µA)

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LV-A

Supply voltage (min) (V)

Supply voltage (max) (V)

5.5

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-16

Supply current (max) (µA)

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOIC (DW)

131.84 mm² 12.8 x 10.3

98.28 mm² 12.6 x 7.8

56.16 mm² 7.2 x 7.8

41.6 mm² 6.5 x 6.4

32 mm² 5 x 6.4

VCC operation of 2V to 5.5V
Max tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mA per JESD 17
Ioff supports live insertion, partial power-down mode, and back drive protection

VCC operation of 2V to 5.5V
Max tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mA per JESD 17
Ioff supports live insertion, partial power-down mode, and back drive protection

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation.

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation.

The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

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