封裝資訊
封裝 | 針腳 TSSOP (PW) | 20 |
操作溫度範圍 (°C) -40 to 125 |
包裝數量 | 運送業者 2,000 | LARGE T&R |
SN74LV240A 的特色
- VCC operation of 2V to 5.5V
- Max tpd of 6.5ns at 5V
- Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
- Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
- Support mixed-mode voltage operation on all ports
- Latch-up performance exceeds 250mA per JESD 17
- Ioff supports live insertion, partial power-down mode, and back drive protection
SN74LV240A 的說明
These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation.
The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.