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非反相緩衝器和驅動器

SN74LV244A

現行

具有三態輸出的八通道 2-V 至 5.5-V 緩衝器

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產品規格表

SN74LV244A

現行
產品規格表 立即訂購

產品詳細資料

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SOP (NS) 20 98.28 mm² 12.6 x 7.8 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4 TVSOP (DGV) 20 32 mm² 5 x 6.4 VQFN (RGY) 20 15.75 mm² 4.5 x 3.5 VQFN (RKS) 20 11.25 mm² 4.5 x 2.5 VSSOP (DGS) 20 24.99 mm² 5.1 x 4.9
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 6.5 ns at 5 V
  • Typical V OLP (output ground bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) >2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250-mA per JESD 17
  • V CC operation of 2 V to 5.5 V
  • Maximum t pd of 6.5 ns at 5 V
  • Typical V OLP (output ground bounce) <0.8 V at V CC = 3.3 V, T A = 25°C
  • Typical V OHV (output V OH undershoot) >2.3 V at V CC = 3.3 V, T A = 25°C
  • Support mixed-mode voltage operation on all ports
  • I off supports partial-power-down mode operation
  • Latch-up performance exceeds 250-mA per JESD 17

The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V V CC operation.

The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable ( OE) inputs.

The SN74LV244A octal buffers and line drivers are designed for 2-V to 5.5-V V CC operation.

The SN74LV244A devices are designed specifically to improve both performance and density of the 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit line drivers with separate output-enable ( OE) inputs.
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* Data sheet SN74LV244A Octal Buffers and Drivers With 3-State Outputs datasheet (Rev. R) PDF | HTML 2023年 8月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
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開發板

14-24-NL-LOGIC-EVM — 適用於 14 針腳至 24 針腳無引線封裝的邏輯產品通用評估模組

14-24-NL-LOGIC-EVM 是一款靈活的評估模組 (EVM)，設計用途可支援任何具有 14 針腳至 24 針腳 BQA、BQB、RGY、RSV、RJW 或 RHL 封裝的邏輯或轉換裝置。

使用指南: PDF | HTML
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模擬型號

SN74LV244A Behavioral SPICE Model

SCEM653.ZIP (7 KB) - PSpice Model
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模擬型號

SN74LV244A IBIS Model (Rev. A)

SCEM137A.ZIP (24 KB) - IBIS Model
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參考設計

TIDEP0022 — 具有整合式 BiSS C 主介面的 ARM MPU 參考設計

Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0035 — 具有整合式 HIPERFACE DSL 主介面的 ARM MPU 參考設計

This reference design implements HIPERFACE DSL master protocol on Industrial Communication Sub-System (PRU-ICSS). The two-wire interface allows integration of position feedback wires into motor cable.  It consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0050 — EnDat 2.2 系統參考設計

This reference design implements EnDat 2.2 Master protocol stack and hardware interface based on HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of EnDat 2.2 Master protocol stack, half-duplex communications using RS-485 transceivers and the line termination (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0054 — 適用於變電所自動化的平行備援通訊協定 (PRP) 乙太網路參考設計

This is a reference design for high-reliability, low-latency network communications for substation automation equipment in smart grid transmission and distribution networks. It supports the parallel redundancy protocol (PRP) specification in the IEC 62439 standard using the PRU-ICSS. This reference (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 20 Ultra Librarian
SOP (NS) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian
TVSOP (DGV) 20 Ultra Librarian
VQFN (RGY) 20 Ultra Librarian
VQFN (RKS) 20 Ultra Librarian
VSSOP (DGS) 20 Ultra Librarian
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