首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 固定方向電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
固定方向電壓轉換器

SN74LV6T07-Q1

現行

具有三態輸出的車用 1.8-V 至 5.5-V 單電源 6 位元緩衝器

立即訂購
產品規格表

SN74LV6T07-Q1

現行
產品規格表 立即訂購

產品詳細資料

Technology family LV1T Applications GPIO, SPI Bits (#) 6 Configuration 6 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Open-drain Rating Automotive Operating temperature range (°C) -40 to 85
Technology family LV1T Applications GPIO, SPI Bits (#) 6 Configuration 6 Ch A to B 0 Ch B to A High input voltage (min) (V) 1 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 200 IOH (max) (mA) -8 IOL (max) (mA) 8 Features Balanced outputs, Single supply Input type TTL-Compatible CMOS Output type Balanced CMOS, Open-drain Rating Automotive Operating temperature range (°C) -40 to 85
TSSOP (PW) 14 32 mm² 5 x 6.4 WQFN (BQA) 14 7.5 mm² 3 x 2.5
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in wettable flank QFN package

  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17
  • AEC-Q100 qualified for automotive applications:
    • Device temperature grade 1: -40°C to +125°C
    • Device HBM ESD classification level 2
    • Device CDM ESD classification level C4B

  • Available in wettable flank QFN package

  • Wide operating range of 1.65 V to 5.5 V
  • 5.5-V tolerant input pins
  • LVxT enhanced inputs combined with open-drain outputs provide maximum voltage translation flexibility:
    • Over 6.67-Mbps operation, (R PU = 1 kΩ, C L = 30 pF)
    • Up translation from 1.2 V to 5 V with 1.8-V supply
    • Down translation from 5 V to 0.8 V or even less with any valid supply
  • 5.5-V tolerant input pins
  • Supports standard function pinout
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74LV6T07-Q1 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV6T07-Q1 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
filter 尋找其它 固定方向電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3
類型 標題 日期
* Data sheet SN74LV6T07-Q1 Automotive Hex Open-Drain Buffers with Integrated Translation datasheet PDF | HTML 2023年 8月 15日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 14 Ultra Librarian
WQFN (BQA) 14 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片