SN74LV8T244-EP
- Wide operating range of 1.65V to 5.5V
- 5.5V tolerant input pins
- Single-supply voltage translator (refer to LVxT Enhanced Input Voltage):
- Up translation:
- 1.2V to 1.8V
- 1.5V to 2.5V
- 1.8V to 3.3V
- 3.3V to 5.0V
-
Down translation:
- 5.0V, 3.3V, 2.5V to 1.8V
- 5.0V, 3.3V to 2.5V
- 5.0V to 3.3V
- Up translation:
- Up to 150Mbps with 5V or 3.3V VCC
- Supports standard function pinout
- Latch-up performance exceeds 250mAper JESD 17
- Operating ambient temperature: -55°C to +125°C
- Supports defense and aerospace applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
The SN74LV8T244-EP is an octal buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks of four drivers, each controlled by an output enable pin.
The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SN74LV8T244-EP Enhanced Product, Octal Buffers and Drivers with 3-State Outputs and Logic-Level Shifter datasheet (Rev. A) | PDF | HTML | 2024年 10月 23日 |
| * | Radiation & reliability report | SN74LV8T244-EP Enhanced Product Qualification and Reliability Report | PDF | HTML | 2024年 10月 9日 |
設計與開發
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開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點