SN74LVC1G240

Name: SN74LVC1G240
Brand: TI
SKU: SN74LVC1G240
Price: 0.084 USD

現行

具有 3 態輸出的單路 1.65-V 至 5.5-V 逆變器

立即訂購

產品規格表

document-pdfAcrobat Single Buffer/Driver With 3-State Output, SN74LVC1G240 datasheet (Rev. L) (英文)

SN74LVC1G240

現行

產品規格表

立即訂購

產品詳細資料

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

1

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Supply voltage (min) (V)

1.65

Supply voltage (max) (V)

5.5

Number of channels

1

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

5

2.1875 mm² 1.75 x 1.25

SOT-23 (DBV)

5

8.12 mm² 2.9 x 2.8

SOT-SC70 (DCK)

5

4.2 mm² 2 x 2.1

USON (DRY)

6

1.45 mm² 1.45 x 1

X2SON (DSF)

6

1 mm² 1 x 1

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-μA Max I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This single buffer/driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single buffer/driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G240 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

filter

尋找其它反相緩衝器和驅動器

下載觀看有字幕稿的影片影片

您可能會感興趣的類似產品

open-in-new

比較替代產品

引腳對引腳且具備與所比較裝置相同的功能

SN74AUP1G14

現行

具有施密特觸發器輸入的單路 0.8-V 至 3.6-V 低功耗逆變器 Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

技術文件

star

=TI 所選的此產品重要文件

找不到結果。請清除您的搜尋條件，然後再試一次。

檢視所有 27

	類型	標題	日期
*	Data sheet	Single Buffer/Driver With 3-State Output, SN74LVC1G240 datasheet (Rev. L)	2013年 12月 12日
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	2021年 7月 26日
	Selection guide	Little Logic Guide 2018 (Rev. G)	2018年 7月 6日
	Selection guide	Logic Guide (Rev. AB)	2017年 6月 12日
	Application note	How to Select Little Logic (Rev. A)	2016年 7月 26日
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	2015年 12月 2日
	User guide	LOGIC Pocket Data Book (Rev. B)	2007年 1月 16日
	Product overview	Design Summary for WCSP Little Logic (Rev. B)	2004年 11月 4日
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	2004年 7月 8日
	Application note	Selecting the Right Level Translation Solution (Rev. A)	2004年 6月 22日
	User guide	Signal Switch Data Book (Rev. A)	2003年 11月 14日
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits	2003年 11月 6日
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)	2002年 12月 18日
	Application note	Texas Instruments Little Logic Application Report	2002年 11月 1日
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	2002年 8月 29日
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	2002年 6月 13日
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	2002年 5月 22日
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	2002年 5月 10日
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	2002年 3月 27日
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices	1997年 12月 1日
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	1997年 8月 1日
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)	1997年 6月 1日
	Application note	LVC Characterization Information	1996年 12月 1日
	Application note	Input and Output Characteristics of Digital Integrated Circuits	1996年 10月 1日
	Application note	Live Insertion	1996年 10月 1日
	Design guide	Low-Voltage Logic (LVC) Designer's Guide	1996年 9月 1日
	Application note	Understanding Advanced Bus-Interface Products Design Guide	1996年 5月 1日