首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 方向控制電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
方向控制電壓轉換器

SN74LVC2T45

現行

具可配置電壓位準移位與 3 態輸出的 2 位元雙供應收發器

立即訂購
產品規格表

SN74LVC2T45

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 420 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family LVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 1.08 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 Data rate (max) (Mbps) 420 IOH (max) (mA) -32 IOL (max) (mA) 32 Supply current (max) (µA) 4 Features Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
  • VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
  • DIR input circuit referenced to VCCA
  • Low power consumption, 4-µA maximum ICC
  • Available in the Texas Instruments NanoFree™ package
  • ±24-mA output drive at 3.3 V
  • Ioff supports Partial-Power-Down mode operation
  • Maximum data rates:
    • 420 Mbps (3.3-V to 5-V translation)
    • 210 Mbps (translate to 3.3 V)
    • 140 Mbps (translate to 2.5 V)
    • 75 Mbps (translate to 1.8 V)
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 5.5V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65V to 5.5V. This allows for universal low-voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports are always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74LVC2T45 is designed so that VCCA supplies the DIR input circuit. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature is designed so that if either VCC input is at GND, both ports are in the high-impedance state.
filter 尋找其它 方向控制電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 32
類型 標題 日期
* Data sheet SN74LVC2T45 Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. N) PDF | HTML 2024年 6月 21日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
EVM User's guide Generic AVC and LVC Direction Controlled Translation EVM (Rev. B) 2021年 7月 30日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
TI.com 無法提供
開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

使用指南: PDF
TI.com 無法提供
模擬型號

SN74LVC2T45 IBIS Model (Rev. A)

SCEM409A.ZIP (95 KB) - IBIS Model
下載
參考設計

TIDM-ULTRASONIC-WATER-FLOW-MEASUREMENT — 超音波水流量測參考設計

This Ultrasonic Water Flow Measurement system is ideal for providing highly accurate measurement across wide flow ranges as low as 1.4gpm. The design is based on a single MCU with discrete analog components. It uses a unique propriety algorithm that improves robustness and performance in flow (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010026 — 適用於 EnDat2.2 絕對編碼器的耐用介面參考設計

This reference design demonstrates a robust interface to EnDat 2.2 Encoders. That shows EMC immunity, particularly immunity against fast transients such as inverter switching noise. The Encoder supply voltage is configurable and integrates protection against short circuit to prevent damage due to (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01630 — 適用於 Tamagawa 編碼器的高 EMC 抗擾性 RS485 介面參考設計

EMC immunity, especially immunity against inverter switching noise, is important for positioning encoder feedback systems of industrial drives. This design demonstrates a high EMC immunity RS485 transceiver solution which can be used on both the drive and encoder, such as Tamagawa™, EnDat (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01401 — 適用於絕對編碼器的高 EMC 耐受性 RS-485 介面參考設計

This high EMC immunity reference design demonstrates a RS-485 transceiver to use on both the drive and within encoders such as: EnDat 2.2, BiSS®, Tamagawa™, etc. EMC immunity, particularly immunity against inverter switching noise, is important for position encoder feedback systems (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YZP) 8 Ultra Librarian
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片