產品詳細資料

Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Partial power down (Ioff), Positive input clamp diode, Very high speed (tpd 5-10ns) Technology family LVT Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PM) 64 144 mm² 12 x 12
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • B-Port Outputs of 'LVTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPE Instruction Set
    • IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

    SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Members of the Texas Instruments WidebusTM Family
  • State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Support Unregulated Battery Operation Down to 2.7 V
  • UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • B-Port Outputs of 'LVTH182504A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
  • Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPE Instruction Set
    • IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

    SCOPE, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

The 'LVTH18504A and 'LVTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the , LEBA,, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

 

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of 'LVTH182504A, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18504A and SN54LVTH182504A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH18504A and SN74LVTH182504A are characterized for operation from -40°C to 85°C.

 

 

 

 

 

The 'LVTH18504A and 'LVTH182504A scan test devices with 20-bit universal bus transceivers are members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable ( and ), latch-enable (LEAB and LEBA), clock-enable ( and ), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and is low, A-bus data is stored on a low-to-high transition of CLKAB. When is low, the B outputs are active. When is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the , LEBA,, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

 

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions, such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of 'LVTH182504A, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

The SN54LVTH18504A and SN54LVTH182504A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVTH18504A and SN74LVTH182504A are characterized for operation from -40°C to 85°C.

 

 

 

 

 

下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 19
類型 標題 日期
* Data sheet 3.3-V ABT Scan Test Devices With 20-Bit Universal Bus Transceivers datasheet (Rev. B) 1997年 6月 1日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
EVM User's guide LASP Demo Board User's Guide 2005年 11月 1日
Application note Programming CPLDs Via the 'LVT8986 LASP 2005年 11月 1日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note LVT-to-LVTH Conversion 1998年 12月 8日
Application note LVT Family Characteristics (Rev. A) 1998年 3月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

BSDL Model of SN74LVTH182504A

SCTM036.ZIP (3 KB) - BSDL Model
模擬型號

SN74LVTH182504A IBIS Model

SCTM049.ZIP (22 KB) - IBIS Model
封裝 針腳 CAD 符號、佔位空間與 3D 模型
LQFP (PM) 64 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片