TXS0101
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- A Port
- 2500 V Human-Body Model (A114-B)
- 200 V Machine Model (A115-A)
- 1500 V Charged-Device Model (C101)
- B Port
- 8 kV Human-Body Model (A114-B)
- 200 V Machine Model (A115-A)
- 1500 V Charged-Device Model (C101)
- A Port
- No Direction-Control Signal Needed
- Maximum Data Rates
- 24 Mbps (Push Pull)
- 2 Mbps (Open Drain)
- Available in the Texas Instruments NanoFree™ Package
- 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B port (VCCA ≤ VCCB)
- VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
- No Power-Supply Sequencing Required – Either VCCA or VCCB Can be Ramped First
- Ioff Supports Partial-Power-Down Mode Operation
This one-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 3.6 V. The B port is designed to track VCCB. VCCA must be less than or equal to VCCB. VCCB accepts any supply voltage from 2.3 V to 5.5 V. This allows for low voltage bidirectional translation between any of the 1.8 V, 2.5 V, 3.3 V, and 5 V voltage nodes.
When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
技術文件
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YZP) | 6 | Ultra Librarian |
SOT-23 (DBV) | 6 | Ultra Librarian |
SOT-5X3 (DRL) | 6 | Ultra Librarian |
SOT-SC70 (DCK) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點