TXS0101
- Latch-up performance exceeds 100mA per JESD 78, class II
- ESD protection exceeds JESD 22:
- A Port:
- 2500V Human-Body Model (A114-B)
- 200V Machine Model (A115-A)
- 1500V Charged-Device Model (C101)
- B port:
- 8kV Human-Body Model (A114-B)
- 200V Machine Model (A115-A)
- 1500V Charged-Device Model (C101)
- A Port:
- No direction-control signal needed
- Maximum data rates:
- 24Mbps (push pull)
- 2Mbps (open drain)
- Available in the Texas Instruments NanoFree™ package
- 1.65V to 3.6V on A port and 2.3V to 5.5V on B port ( VCCA ≤ VCCB)
- VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
- No power-supply sequencing required – either VCCA or VCCB can be ramped first
- Ioff supports partial-power-down mode operation
This one-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65V to 3.6V. VCCA must be less than or equal to VCCB . The B port is designed to track VCCB. VCCB accepts any supply voltage from 2.3V to 5.5V. This allows for low voltage bidirectional translation between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.
When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.
To put the device in the high-impedance state during power up or power down, tie OE to GND through a pull-down resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.
技術文件
設計與開發
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5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YZP) | 6 | Ultra Librarian |
SOT-23 (DBV) | 6 | Ultra Librarian |
SOT-5X3 (DRL) | 6 | Ultra Librarian |
SOT-SC70 (DCK) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點