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自動方向電壓轉換器
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TXS0102V

現行

適用於汲極斷路和推拉應用的二位元雙向位準移位器

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產品規格表

TXS0102V

現行
產品規格表 立即訂購

產品詳細資料

Technology family TXS Applications I2C, MDIO Bits (#) 2 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Partial power down (Ioff), Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
Technology family TXS Applications I2C, MDIO Bits (#) 2 Data rate (max) (Mbps) 24 High input voltage (min) (V) 1.45 High input voltage (max) (V) 5.5 Vout (min) (V) 1.65 Vout (max) (V) 5.5 IOH (max) (mA) 0 IOL (max) (mA) 0 Supply current (max) (µA) 10 Features Edge rate accelerator, Output enable, Partial power down (Ioff), Vcc isolation Input type Transmission Gate Output type 3-State, Transmission Gate Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • No direction-control signal needed
  • Maximum data rates:
    • 24 Mbps (push pull)
    • 2 Mbps (open drain)
  • Available in the Texas Instruments NanoStar™ integrated circuit package
  • 1.65V to 3.6V on A port and 2.3V to 5.5V on B port (VCCA ≤ VCCB)
  • VCC isolation feature: if either VCC input is at GND, both ports are in the High-Impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
    • B port:
      • 5000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
  • No direction-control signal needed
  • Maximum data rates:
    • 24 Mbps (push pull)
    • 2 Mbps (open drain)
  • Available in the Texas Instruments NanoStar™ integrated circuit package
  • 1.65V to 3.6V on A port and 2.3V to 5.5V on B port (VCCA ≤ VCCB)
  • VCC isolation feature: if either VCC input is at GND, both ports are in the High-Impedance state
  • No power-supply sequencing required: either VCCA or VCCB can be ramped first
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • A port:
      • 2000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)
    • B port:
      • 5000V Human-Body Model (A114-B)
      • 500V Charged-Device Model (C101)

This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails, with the A ports supporting operating voltages from 1.65V to 3.6V while it tracks the VCCA supply, and the B ports supporting operating voltages from 2.3V to 5.5V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption.

To put the device in the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.

This two-bit non-inverting translator is a bidirectional voltage-level translator and can be used to establish digital switching compatibility between mixed-voltage systems. It uses two separate configurable power-supply rails, with the A ports supporting operating voltages from 1.65V to 3.6V while it tracks the VCCA supply, and the B ports supporting operating voltages from 2.3V to 5.5V while it tracks the VCCB supply. This allows the support of both lower and higher logic signal levels while providing bidirectional translation capabilities between any of the 1.8V, 2.5V, 3.3V, and 5V voltage nodes.

When the output-enable (OE) input is low, all I/Os are placed in the high-impedance state, which significantly reduces the power-supply quiescent current consumption.

To put the device in the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the current-sourcing capability of the driver determines the minimum value of the resistor.
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* Data sheet TXS0102V 2-Bit Bi-Directional, Level-Shifting, Voltage Translator for Open-Drain and Push-Pull Applications datasheet PDF | HTML 2024年 6月 24日

設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

TXS-EVM — 適用於單通道、雙通道、四通道和八通道裝置的轉換器系列評估模組

TXS-EVM 旨在支援單通道、雙通道、四通道和八通道 TXS 裝置。TXS 產品屬於自動雙向電壓位準轉換系列，運作電壓介於 1.2V 與 5.5 V，旨在支援不同產業中的各種通用電壓位準轉換應用。

使用指南: PDF | HTML
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SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
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  • 進行中持續性的可靠性監測
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